diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 8548d612129..cc154c4be01 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -436,7 +436,7 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L, SmallVector<MachineOperand,2> Cond; MachineBasicBlock *TB = nullptr, *FB = nullptr; - bool NotAnalyzed = TII->AnalyzeBranch(*ExitingBlock, TB, FB, Cond, false); + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); if (NotAnalyzed) return false; @@ -583,7 +583,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, SmallVector<MachineOperand,2> Cond; MachineBasicBlock *TB = nullptr, *FB = nullptr; - bool NotAnalyzed = TII->AnalyzeBranch(*ExitingBlock, TB, FB, Cond, false); + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); if (NotAnalyzed) return nullptr; @@ -595,7 +595,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { MachineBasicBlock *LTB = 0, *LFB = 0; SmallVector<MachineOperand,2> LCond; - bool NotAnalyzed = TII->AnalyzeBranch(*Latch, LTB, LFB, LCond, false); + bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false); if (NotAnalyzed) return nullptr; if (TB == Latch) @@ -1186,7 +1186,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L, MachineBasicBlock *TB = 0, *FB = 0; SmallVector<MachineOperand, 2> Cond; - if (TII->AnalyzeBranch(*ExitingBlock, TB, FB, Cond, false)) + if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false)) return false; if (L->contains(TB)) @@ -1425,7 +1425,7 @@ bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow( MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector<MachineOperand, 2> Cond; - if (TII->AnalyzeBranch(*MI->getParent(), TBB, FBB, Cond, false)) + if (TII->analyzeBranch(*MI->getParent(), TBB, FBB, Cond, false)) continue; Comparison::Kind Cmp = getComparisonKind(MI->getOpcode(), 0, 0, 0); @@ -1621,14 +1621,14 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { MachineBasicBlock *TB = nullptr, *FB = nullptr; SmallVector<MachineOperand,2> Cond; // AnalyzeBranch returns true if it fails to analyze branch. - bool NotAnalyzed = TII->AnalyzeBranch(*ExitingBlock, TB, FB, Cond, false); + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); if (NotAnalyzed || Cond.empty()) return false; if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { MachineBasicBlock *LTB = 0, *LFB = 0; SmallVector<MachineOperand,2> LCond; - bool NotAnalyzed = TII->AnalyzeBranch(*Latch, LTB, LFB, LCond, false); + bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false); if (NotAnalyzed) return false; @@ -1839,12 +1839,12 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( SmallVector<MachineOperand,2> Tmp1; MachineBasicBlock *TB = nullptr, *FB = nullptr; - if (TII->AnalyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) + if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) return nullptr; for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) { MachineBasicBlock *PB = *I; - bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false); + bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false); if (NotAnalyzed) return nullptr; } @@ -1930,7 +1930,7 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( MachineBasicBlock *PB = *I; if (PB != Latch) { Tmp2.clear(); - bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp2, false); + bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false); (void)NotAnalyzed; // suppress compiler warning assert (!NotAnalyzed && "Should be analyzable!"); if (TB != Header && (Tmp2.empty() || FB != Header)) @@ -1942,7 +1942,7 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( // It can happen that the latch block will fall through into the header. // Insert an unconditional branch to the header. TB = FB = nullptr; - bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false); + bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false); (void)LatchNotAnalyzed; // suppress compiler warning assert (!LatchNotAnalyzed && "Should be analyzable!"); if (!TB && !FB) |
