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path: root/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
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* Sink all InitializePasses.h includesReid Kleckner2019-11-131-0/+1
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-26/+26
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-2/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* Don't create a temporary vector of loop blocks just to iterate over them.Benjamin Kramer2018-09-101-8/+6
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-10/+11
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-26/+26
* [Hexagon] Handle subregisters when calculating iteration count in HW loopsKrzysztof Parzyszek2018-04-061-0/+1
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-1/+1
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-2/+2
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-3/+3
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-1/+1
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-1/+1
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-201-6/+20
* [Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek2017-10-201-7/+11
* [llvm] Fix some typos. NFC.Mandeep Singh Grang2017-09-151-1/+1
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-1/+1
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko2017-07-291-16/+25
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-171-12/+12
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-171-11/+11
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-161-11/+11
* Fix "left shift of negative value -1" introduced by r294805Vitaly Buka2017-02-111-1/+1
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko2016-12-161-16/+37
* Fix spelling mistakes in Hexagon target comments. NFC.Simon Pilgrim2016-11-171-1/+1
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-4/+4
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-4/+4
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-6/+2
* Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2016-09-131-2/+6
* This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2016-09-131-6/+2
* MachineLoop: add methods findLoopControlBlock and findLoopPreheaderSjoerd Meijer2016-08-151-62/+11
* [Hexagon] Allow non-returning calls in hardware loopsKrzysztof Parzyszek2016-08-111-2/+2
* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-2/+2
* [Hexagon] Find speculative loop preheader in hardware loop generationKrzysztof Parzyszek2016-07-271-10/+57
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-11/+11
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-5/+5
* Add optimization bisect opt-in calls for Hexagon passesAndrew Kaylor2016-04-261-0/+2
* Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"Duncan P. N. Exon Smith2016-02-221-2/+2
* CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFCDuncan P. N. Exon Smith2016-02-211-2/+2
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-6/+4
* Fix some comment typos.Benjamin Kramer2015-08-081-3/+3
* [Hexagon] Moving pass declarations out of header and in to implementation fil...Colin LeMahieu2015-06-151-0/+1
* [Hexagon] Generate hardware loop for a vectorized loopBrendon Cahoon2015-05-141-7/+46
* [Hexagon] Remove dead constant assignment in hardware loop passBrendon Cahoon2015-05-141-3/+9
* [Hexagon] Check for underflow/wrap in hardware loop passBrendon Cahoon2015-05-141-55/+307
* [Hexagon] Generate loop1 instruction for nested loopsBrendon Cahoon2015-05-131-56/+83
* [Hexagon] Generate hardware loop when loop has a critical edgeBrendon Cahoon2015-05-131-13/+37
* [Hexagon] Generate more hardware loopsBrendon Cahoon2015-05-081-133/+206
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