diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index c1f32e54e98..36a5fadc781 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -385,7 +385,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) if (!MO.isReg() || !MO.isDef()) continue; unsigned R = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(R)) + if (!Register::isVirtualRegister(R)) continue; if (!isPredicate(R)) continue; @@ -402,7 +402,7 @@ bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const { if (!MO.isReg() || !MO.isUse()) continue; unsigned R = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(R)) + if (!Register::isVirtualRegister(R)) continue; const MachineInstr *DefI = MRI->getVRegDef(R); // "Undefined" virtual registers are actually defined via IMPLICIT_DEF. @@ -492,7 +492,7 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs( if (!MO.isReg() || !MO.isDef()) continue; unsigned R = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(R)) + if (!Register::isVirtualRegister(R)) continue; if (isPredicate(R)) PredDefs++; |
