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-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index ef0f18b39f9..063aaa7af3d 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -896,6 +896,7 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
*MRI.getTargetRegisterInfo());
auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
+ (void)HRI;
assert(Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo) ||
Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
};
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