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Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp38
1 files changed, 19 insertions, 19 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index d33d179616a..3068fb6f962 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -290,7 +290,7 @@ void HexagonBitSimplify::getInstrDefs(const MachineInstr &MI,
for (auto &Op : MI.operands()) {
if (!Op.isReg() || !Op.isDef())
continue;
- unsigned R = Op.getReg();
+ Register R = Op.getReg();
if (!Register::isVirtualRegister(R))
continue;
Defs.insert(R);
@@ -302,7 +302,7 @@ void HexagonBitSimplify::getInstrUses(const MachineInstr &MI,
for (auto &Op : MI.operands()) {
if (!Op.isReg() || !Op.isUse())
continue;
- unsigned R = Op.getReg();
+ Register R = Op.getReg();
if (!Register::isVirtualRegister(R))
continue;
Uses.insert(R);
@@ -976,7 +976,7 @@ bool DeadCodeElimination::isDead(unsigned R) const {
continue;
if (UseI->isPHI()) {
assert(!UseI->getOperand(0).getSubReg());
- unsigned DR = UseI->getOperand(0).getReg();
+ Register DR = UseI->getOperand(0).getReg();
if (DR == R)
continue;
}
@@ -1015,7 +1015,7 @@ bool DeadCodeElimination::runOnNode(MachineDomTreeNode *N) {
for (auto &Op : MI->operands()) {
if (!Op.isReg() || !Op.isDef())
continue;
- unsigned R = Op.getReg();
+ Register R = Op.getReg();
if (!Register::isVirtualRegister(R) || !isDead(R)) {
AllDead = false;
break;
@@ -1217,7 +1217,7 @@ bool RedundantInstrElimination::computeUsedBits(unsigned Reg, BitVector &Bits) {
return false;
MachineInstr &UseI = *I->getParent();
if (UseI.isPHI() || UseI.isCopy()) {
- unsigned DefR = UseI.getOperand(0).getReg();
+ Register DefR = UseI.getOperand(0).getReg();
if (!Register::isVirtualRegister(DefR))
return false;
Pending.push_back(DefR);
@@ -1342,7 +1342,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
// If found, replace the instruction with a COPY.
const DebugLoc &DL = MI->getDebugLoc();
const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
- unsigned NewR = MRI.createVirtualRegister(FRC);
+ Register NewR = MRI.createVirtualRegister(FRC);
MachineInstr *CopyI =
BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
.addReg(RS.Reg, 0, RS.Sub);
@@ -1409,7 +1409,7 @@ bool ConstGeneration::isTfrConst(const MachineInstr &MI) {
// register class and the actual value being transferred.
unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C,
MachineBasicBlock &B, MachineBasicBlock::iterator At, DebugLoc &DL) {
- unsigned Reg = MRI.createVirtualRegister(RC);
+ Register Reg = MRI.createVirtualRegister(RC);
if (RC == &Hexagon::IntRegsRegClass) {
BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), Reg)
.addImm(int32_t(C));
@@ -1606,7 +1606,7 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
auto *FRC = HBS::getFinalVRegClass(R, MRI);
if (findMatch(R, MR, AVB)) {
- unsigned NewR = MRI.createVirtualRegister(FRC);
+ Register NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
.addReg(MR.Reg, 0, MR.Sub);
BT.put(BitTracker::RegisterRef(NewR), BT.get(MR));
@@ -1625,7 +1625,7 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
BitTracker::RegisterRef ML, MH;
if (findMatch(TL, ML, AVB) && findMatch(TH, MH, AVB)) {
auto *FRC = HBS::getFinalVRegClass(R, MRI);
- unsigned NewR = MRI.createVirtualRegister(FRC);
+ Register NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, At, DL, HII.get(TargetOpcode::REG_SEQUENCE), NewR)
.addReg(ML.Reg, 0, ML.Sub)
.addImm(SubLo)
@@ -2022,7 +2022,7 @@ bool BitSimplification::genPackhl(MachineInstr *MI,
return false;
MachineBasicBlock &B = *MI->getParent();
- unsigned NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
+ Register NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
DebugLoc DL = MI->getDebugLoc();
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
@@ -2094,7 +2094,7 @@ bool BitSimplification::genCombineHalf(MachineInstr *MI,
MachineBasicBlock &B = *MI->getParent();
DebugLoc DL = MI->getDebugLoc();
- unsigned NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
+ Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
BuildMI(B, At, DL, HII.get(COpc), NewR)
@@ -2151,7 +2151,7 @@ bool BitSimplification::genExtractLow(MachineInstr *MI,
if (!validateReg(RS, NewOpc, 1))
continue;
- unsigned NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
+ Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR)
@@ -2365,7 +2365,7 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI,
return true;
}
} else if (V.is(0) || V.is(1)) {
- unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
+ Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
unsigned NewOpc = V.is(0) ? Hexagon::PS_false : Hexagon::PS_true;
BuildMI(B, At, DL, HII.get(NewOpc), NewR);
HBS::replaceReg(RD.Reg, NewR, MRI);
@@ -2538,7 +2538,7 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
DebugLoc DL = MI->getDebugLoc();
MachineBasicBlock &B = *MI->getParent();
- unsigned NewR = MRI.createVirtualRegister(FRC);
+ Register NewR = MRI.createVirtualRegister(FRC);
auto At = MI->isPHI() ? B.getFirstNonPHI()
: MachineBasicBlock::iterator(MI);
auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
@@ -2609,8 +2609,8 @@ bool BitSimplification::simplifyRCmp0(MachineInstr *MI,
KnownNZ = true;
}
- auto ReplaceWithConst = [&] (int C) {
- unsigned NewR = MRI.createVirtualRegister(FRC);
+ auto ReplaceWithConst = [&](int C) {
+ Register NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), NewR)
.addImm(C);
HBS::replaceReg(RD.Reg, NewR, MRI);
@@ -2675,7 +2675,7 @@ bool BitSimplification::simplifyRCmp0(MachineInstr *MI,
// replace the comparison with a C2_muxii, using the same predicate
// register, but with operands substituted with 0/1 accordingly.
if ((KnownZ1 || KnownNZ1) && (KnownZ2 || KnownNZ2)) {
- unsigned NewR = MRI.createVirtualRegister(FRC);
+ Register NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, At, DL, HII.get(Hexagon::C2_muxii), NewR)
.addReg(InpDef->getOperand(1).getReg())
.addImm(KnownZ1 == (Opc == Hexagon::A4_rcmpeqi))
@@ -3068,7 +3068,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
DenseMap<unsigned,unsigned> RegMap;
const TargetRegisterClass *PhiRC = MRI->getRegClass(NewPredR);
- unsigned PhiR = MRI->createVirtualRegister(PhiRC);
+ Register PhiR = MRI->createVirtualRegister(PhiRC);
BuildMI(LB, At, At->getDebugLoc(), HII->get(TargetOpcode::PHI), PhiR)
.addReg(NewPredR)
.addMBB(&PB)
@@ -3080,7 +3080,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
const MachineInstr *SI = G.Ins[i-1];
unsigned DR = getDefReg(SI);
const TargetRegisterClass *RC = MRI->getRegClass(DR);
- unsigned NewDR = MRI->createVirtualRegister(RC);
+ Register NewDR = MRI->createVirtualRegister(RC);
DebugLoc DL = SI->getDebugLoc();
auto MIB = BuildMI(LB, At, DL, HII->get(SI->getOpcode()), NewDR);
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