diff options
Diffstat (limited to 'llvm/lib/Target/Alpha')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaInstrInfo.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaInstrInfo.h | 2 |
2 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp index ec8857fc7f4..b566de45105 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -133,15 +133,15 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, return 2; } -void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); + // Not yet supported! + return false; } if (DestRC == Alpha::GPRCRegisterClass) { @@ -151,9 +151,11 @@ void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, } else if (DestRC == Alpha::F8RCRegisterClass) { BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); + // Attempt to copy register that is not GPR or FPR + return false; } + + return true; } void diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.h b/llvm/lib/Target/Alpha/AlphaInstrInfo.h index ccfa429b8a2..9aa5ecd74c7 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.h +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.h @@ -42,7 +42,7 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, |
