diff options
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/NEONPreAllocPass.cpp | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index c68c645c2cb..efa6e48b055 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1454,6 +1454,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case MVT::v4i16: Opc = ARM::VLD4d16; break; case MVT::v2f32: case MVT::v2i32: Opc = ARM::VLD4d32; break; + case MVT::v1i64: Opc = ARM::VLD4d64; break; } SDValue Chain = N->getOperand(0); const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain }; diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index e7601b2346a..d3aeeed192b 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -247,6 +247,10 @@ class VLD4WB<bits<4> op7_4, string OpcodeStr> def VLD4d8 : VLD4D<0b0000, "vld4.8">; def VLD4d16 : VLD4D<0b0100, "vld4.16">; def VLD4d32 : VLD4D<0b1000, "vld4.32">; +def VLD4d64 : NLdSt<0,0b10,0b0010,0b1100, + (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), + (ins addrmode6:$addr), IIC_VLD1, + "vld1.64\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr", "", []>; // vld4 to double-spaced even registers. def VLD4q8a : VLD4WB<0b0000, "vld4.8">; diff --git a/llvm/lib/Target/ARM/NEONPreAllocPass.cpp b/llvm/lib/Target/ARM/NEONPreAllocPass.cpp index 52a43aaccfd..5de2810f33d 100644 --- a/llvm/lib/Target/ARM/NEONPreAllocPass.cpp +++ b/llvm/lib/Target/ARM/NEONPreAllocPass.cpp @@ -96,6 +96,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs, case ARM::VLD4d8: case ARM::VLD4d16: case ARM::VLD4d32: + case ARM::VLD4d64: case ARM::VLD4LNd8: case ARM::VLD4LNd16: case ARM::VLD4LNd32: |
