diff options
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64ISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64ISelLowering.h | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64ISelLowering.h b/llvm/lib/Target/ARM64/ARM64ISelLowering.h index ebecedccd5a..ddaf347bf1a 100644 --- a/llvm/lib/Target/ARM64/ARM64ISelLowering.h +++ b/llvm/lib/Target/ARM64/ARM64ISelLowering.h @@ -183,7 +183,7 @@ public: /// KnownZero/KnownOne bitsets. void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, - unsigned Depth = 0) const; + unsigned Depth = 0) const override; MVT getScalarShiftAmountTy(EVT LHSTy) const override; @@ -383,33 +383,36 @@ private: SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; - ConstraintType getConstraintType(const std::string &Constraint) const; + ConstraintType + getConstraintType(const std::string &Constraint) const override; /// Examine constraint string and operand type and determine a weight value. /// The operand object must already have been set up with the operand type. - ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, - const char *constraint) const; + ConstraintWeight + getSingleConstraintMatchWeight(AsmOperandInfo &info, + const char *constraint) const override; std::pair<unsigned, const TargetRegisterClass *> - getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; + getRegForInlineAsmConstraint(const std::string &Constraint, + MVT VT) const override; void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, - SelectionDAG &DAG) const; + SelectionDAG &DAG) const override; - bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; - bool mayBeEmittedAsTailCall(CallInst *CI) const; + bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; + bool mayBeEmittedAsTailCall(CallInst *CI) const override; bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const; bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, - SelectionDAG &DAG) const; + SelectionDAG &DAG) const override; bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, - SelectionDAG &DAG) const; + SelectionDAG &DAG) const override; void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, - SelectionDAG &DAG) const; + SelectionDAG &DAG) const override; }; namespace ARM64 { |
