diff options
27 files changed, 141 insertions, 132 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64AddressTypePromotion.cpp b/llvm/lib/Target/ARM64/ARM64AddressTypePromotion.cpp index c6e45def9a4..be2b5eed2ad 100644 --- a/llvm/lib/Target/ARM64/ARM64AddressTypePromotion.cpp +++ b/llvm/lib/Target/ARM64/ARM64AddressTypePromotion.cpp @@ -75,13 +75,13 @@ public: initializeARM64AddressTypePromotionPass(*PassRegistry::getPassRegistry()); } - virtual const char *getPassName() const { + const char *getPassName() const override { return "ARM64 Address Type Promotion"; } /// Iterate over the functions and promote the computation of interesting // sext instructions. - bool runOnFunction(Function &F); + bool runOnFunction(Function &F) override; private: /// The current function. @@ -91,7 +91,7 @@ private: Type *ConsideredSExtType; // This transformation requires dominator info. - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addRequired<DominatorTreeWrapperPass>(); AU.addPreserved<DominatorTreeWrapperPass>(); diff --git a/llvm/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp b/llvm/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp index 87eec8f6160..da280f8be08 100644 --- a/llvm/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp +++ b/llvm/lib/Target/ARM64/ARM64AdvSIMDScalarPass.cpp @@ -87,13 +87,13 @@ public: static char ID; // Pass identification, replacement for typeid. explicit ARM64AdvSIMDScalar() : MachineFunctionPass(ID) {} - virtual bool runOnMachineFunction(MachineFunction &F); + bool runOnMachineFunction(MachineFunction &F) override; - const char *getPassName() const { + const char *getPassName() const override { return "AdvSIMD Scalar Operation Optimization"; } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp b/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp index 615cb2884d2..bc6fef1aa43 100644 --- a/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp +++ b/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp @@ -56,7 +56,7 @@ public: MCInstLowering(OutContext, *Mang, *this), SM(*this), ARM64FI(nullptr), LOHLabelCounter(0) {} - virtual const char *getPassName() const { return "ARM64 Assembly Printer"; } + const char *getPassName() const override { return "ARM64 Assembly Printer"; } /// \brief Wrapper for MCInstLowering.lowerOperand() for the /// tblgen'erated pseudo lowering. @@ -73,14 +73,14 @@ public: bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI); - void EmitInstruction(const MachineInstr *MI); + void EmitInstruction(const MachineInstr *MI) override; - void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AsmPrinter::getAnalysisUsage(AU); AU.setPreservesAll(); } - bool runOnMachineFunction(MachineFunction &F) { + bool runOnMachineFunction(MachineFunction &F) override { ARM64FI = F.getInfo<ARM64FunctionInfo>(); return AsmPrinter::runOnMachineFunction(F); } @@ -95,17 +95,17 @@ private: bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, - raw_ostream &O); + raw_ostream &O) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, - raw_ostream &O); + raw_ostream &O) override; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); - void EmitFunctionBodyEnd(); + void EmitFunctionBodyEnd() override; - MCSymbol *GetCPISymbol(unsigned CPID) const; - void EmitEndOfAsmFile(Module &M); + MCSymbol *GetCPISymbol(unsigned CPID) const override; + void EmitEndOfAsmFile(Module &M) override; ARM64FunctionInfo *ARM64FI; /// \brief Emit the LOHs contained in ARM64FI. diff --git a/llvm/lib/Target/ARM64/ARM64BranchRelaxation.cpp b/llvm/lib/Target/ARM64/ARM64BranchRelaxation.cpp index 06c6733ee6f..cbe97edde27 100644 --- a/llvm/lib/Target/ARM64/ARM64BranchRelaxation.cpp +++ b/llvm/lib/Target/ARM64/ARM64BranchRelaxation.cpp @@ -94,9 +94,9 @@ public: static char ID; ARM64BranchRelaxation() : MachineFunctionPass(ID) {} - virtual bool runOnMachineFunction(MachineFunction &MF); + bool runOnMachineFunction(MachineFunction &MF) override; - virtual const char *getPassName() const { + const char *getPassName() const override { return "ARM64 branch relaxation pass"; } }; diff --git a/llvm/lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp b/llvm/lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp index e3f82487518..dce1301b92e 100644 --- a/llvm/lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp +++ b/llvm/lib/Target/ARM64/ARM64CleanupLocalDynamicTLSPass.cpp @@ -38,7 +38,7 @@ struct LDTLSCleanup : public MachineFunctionPass { static char ID; LDTLSCleanup() : MachineFunctionPass(ID) {} - virtual bool runOnMachineFunction(MachineFunction &MF) { + bool runOnMachineFunction(MachineFunction &MF) override { ARM64FunctionInfo *AFI = MF.getInfo<ARM64FunctionInfo>(); if (AFI->getNumLocalDynamicTLSAccesses() < 2) { // No point folding accesses if there isn't at least two. @@ -129,11 +129,11 @@ struct LDTLSCleanup : public MachineFunctionPass { return Copy; } - virtual const char *getPassName() const { + const char *getPassName() const override { return "Local Dynamic TLS Access Clean-up"; } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addRequired<MachineDominatorTree>(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/Target/ARM64/ARM64CollectLOH.cpp b/llvm/lib/Target/ARM64/ARM64CollectLOH.cpp index 7b8a270b897..8b48f3ae9b2 100644 --- a/llvm/lib/Target/ARM64/ARM64CollectLOH.cpp +++ b/llvm/lib/Target/ARM64/ARM64CollectLOH.cpp @@ -174,13 +174,13 @@ struct ARM64CollectLOH : public MachineFunctionPass { initializeARM64CollectLOHPass(*PassRegistry::getPassRegistry()); } - virtual bool runOnMachineFunction(MachineFunction &MF); + bool runOnMachineFunction(MachineFunction &MF) override; - virtual const char *getPassName() const { + const char *getPassName() const override { return "ARM64 Collect Linker Optimization Hint (LOH)"; } - void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); AU.addRequired<MachineDominatorTree>(); diff --git a/llvm/lib/Target/ARM64/ARM64ConditionalCompares.cpp b/llvm/lib/Target/ARM64/ARM64ConditionalCompares.cpp index 16324ffa77b..ae756c683d3 100644 --- a/llvm/lib/Target/ARM64/ARM64ConditionalCompares.cpp +++ b/llvm/lib/Target/ARM64/ARM64ConditionalCompares.cpp @@ -736,9 +736,11 @@ class ARM64ConditionalCompares : public MachineFunctionPass { public: static char ID; ARM64ConditionalCompares() : MachineFunctionPass(ID) {} - void getAnalysisUsage(AnalysisUsage &AU) const; - bool runOnMachineFunction(MachineFunction &MF); - const char *getPassName() const { return "ARM64 Conditional Compares"; } + void getAnalysisUsage(AnalysisUsage &AU) const override; + bool runOnMachineFunction(MachineFunction &MF) override; + const char *getPassName() const override { + return "ARM64 Conditional Compares"; + } private: bool tryConvert(MachineBasicBlock *); diff --git a/llvm/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp index eded8bd9e64..e8f03ec833f 100644 --- a/llvm/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp +++ b/llvm/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp @@ -36,11 +36,11 @@ public: static char ID; // Pass identification, replacement for typeid. explicit ARM64DeadRegisterDefinitions() : MachineFunctionPass(ID) {} - virtual bool runOnMachineFunction(MachineFunction &F); + virtual bool runOnMachineFunction(MachineFunction &F) override; - const char *getPassName() const { return "Dead register definitions"; } + const char *getPassName() const override { return "Dead register definitions"; } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + virtual void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp b/llvm/lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp index 7928c7e586e..a4b5d31314e 100644 --- a/llvm/lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM64/ARM64ExpandPseudoInsts.cpp @@ -29,9 +29,9 @@ public: const ARM64InstrInfo *TII; - virtual bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; - virtual const char *getPassName() const { + const char *getPassName() const override { return "ARM64 pseudo instruction expansion pass"; } diff --git a/llvm/lib/Target/ARM64/ARM64FastISel.cpp b/llvm/lib/Target/ARM64/ARM64FastISel.cpp index 459c48030f4..560520e90a5 100644 --- a/llvm/lib/Target/ARM64/ARM64FastISel.cpp +++ b/llvm/lib/Target/ARM64/ARM64FastISel.cpp @@ -147,8 +147,8 @@ private: public: // Backend specific FastISel code. - virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI); - virtual unsigned TargetMaterializeConstant(const Constant *C); + unsigned TargetMaterializeAlloca(const AllocaInst *AI) override; + unsigned TargetMaterializeConstant(const Constant *C) override; explicit ARM64FastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) @@ -157,7 +157,7 @@ public: Context = &funcInfo.Fn->getContext(); } - virtual bool TargetSelectInstruction(const Instruction *I); + bool TargetSelectInstruction(const Instruction *I) override; #include "ARM64GenFastISel.inc" }; diff --git a/llvm/lib/Target/ARM64/ARM64FrameLowering.h b/llvm/lib/Target/ARM64/ARM64FrameLowering.h index 02edcdb5904..1991a0a18dd 100644 --- a/llvm/lib/Target/ARM64/ARM64FrameLowering.h +++ b/llvm/lib/Target/ARM64/ARM64FrameLowering.h @@ -36,38 +36,38 @@ public: unsigned FramePtr) const; void eliminateCallFramePseudoInstr(MachineFunction &MF, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const; + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const override; /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; + void emitPrologue(MachineFunction &MF) const override; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; - int getFrameIndexOffset(const MachineFunction &MF, int FI) const; + int getFrameIndexOffset(const MachineFunction &MF, int FI) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const; + unsigned &FrameReg) const override; int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP = false) const; bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const; + const TargetRegisterInfo *TRI) const override; bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const; + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const override; /// \brief Can this function use the red zone for local allocations. bool canUseRedZone(const MachineFunction &MF) const; - bool hasFP(const MachineFunction &MF) const; - bool hasReservedCallFrame(const MachineFunction &MF) const; + bool hasFP(const MachineFunction &MF) const override; + bool hasReservedCallFrame(const MachineFunction &MF) const override; void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const; + RegScavenger *RS) const override; }; } // End llvm namespace diff --git a/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp b/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp index 2971cba362f..07e47e0f54c 100644 --- a/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp @@ -47,11 +47,11 @@ public: : SelectionDAGISel(tm, OptLevel), TM(tm), Subtarget(&TM.getSubtarget<ARM64Subtarget>()), ForCodeSize(false) {} - virtual const char *getPassName() const { + const char *getPassName() const override { return "ARM64 Instruction Selection"; } - virtual bool runOnMachineFunction(MachineFunction &MF) { + bool runOnMachineFunction(MachineFunction &MF) override { AttributeSet FnAttrs = MF.getFunction()->getAttributes(); ForCodeSize = FnAttrs.hasAttribute(AttributeSet::FunctionIndex, @@ -60,13 +60,13 @@ public: return SelectionDAGISel::runOnMachineFunction(MF); } - SDNode *Select(SDNode *Node); + SDNode *Select(SDNode *Node) override; /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. - virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, - char ConstraintCode, - std::vector<SDValue> &OutOps); + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + char ConstraintCode, + std::vector<SDValue> &OutOps) override; SDNode *SelectMLAV64LaneV128(SDNode *N); SDNode *SelectMULLV64LaneV128(unsigned IntNo, SDNode *N); diff --git a/llvm/lib/Target/ARM64/ARM64ISelLowering.h b/llvm/lib/Target/ARM64/ARM64ISelLowering.h index ebecedccd5a..ddaf347bf1a 100644 --- a/llvm/lib/Target/ARM64/ARM64ISelLowering.h +++ b/llvm/lib/Target/ARM64/ARM64ISelLowering.h @@ -183,7 +183,7 @@ public: /// KnownZero/KnownOne bitsets. void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, - unsigned Depth = 0) const; + unsigned Depth = 0) const override; MVT getScalarShiftAmountTy(EVT LHSTy) const override; @@ -383,33 +383,36 @@ private: SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; - ConstraintType getConstraintType(const std::string &Constraint) const; + ConstraintType + getConstraintType(const std::string &Constraint) const override; /// Examine constraint string and operand type and determine a weight value. /// The operand object must already have been set up with the operand type. - ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, - const char *constraint) const; + ConstraintWeight + getSingleConstraintMatchWeight(AsmOperandInfo &info, + const char *constraint) const override; std::pair<unsigned, const TargetRegisterClass *> - getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; + getRegForInlineAsmConstraint(const std::string &Constraint, + MVT VT) const override; void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, - SelectionDAG &DAG) const; + SelectionDAG &DAG) const override; - bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; - bool mayBeEmittedAsTailCall(CallInst *CI) const; + bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; + bool mayBeEmittedAsTailCall(CallInst *CI) const override; bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const; bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, - SelectionDAG &DAG) const; + SelectionDAG &DAG) const override; bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, - SelectionDAG &DAG) const; + SelectionDAG &DAG) const override; void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, - SelectionDAG &DAG) const; + SelectionDAG &DAG) const override; }; namespace ARM64 { diff --git a/llvm/lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp b/llvm/lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp index 54a642917a0..da7a8cd3d90 100644 --- a/llvm/lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM64/ARM64LoadStoreOptimizer.cpp @@ -101,9 +101,9 @@ struct ARM64LoadStoreOpt : public MachineFunctionPass { bool optimizeBlock(MachineBasicBlock &MBB); - virtual bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; - virtual const char *getPassName() const { + const char *getPassName() const override { return "ARM64 load / store optimization pass"; } diff --git a/llvm/lib/Target/ARM64/ARM64PromoteConstant.cpp b/llvm/lib/Target/ARM64/ARM64PromoteConstant.cpp index 2eef90d6cfc..e61a62262d3 100644 --- a/llvm/lib/Target/ARM64/ARM64PromoteConstant.cpp +++ b/llvm/lib/Target/ARM64/ARM64PromoteConstant.cpp @@ -87,11 +87,11 @@ public: static char ID; ARM64PromoteConstant() : ModulePass(ID) {} - virtual const char *getPassName() const { return "ARM64 Promote Constant"; } + const char *getPassName() const override { return "ARM64 Promote Constant"; } /// Iterate over the functions and promote the interesting constants into /// global variables with module scope. - bool runOnModule(Module &M) { + bool runOnModule(Module &M) override { DEBUG(dbgs() << getPassName() << '\n'); bool Changed = false; for (auto &MF : M) { @@ -107,7 +107,7 @@ private: bool runOnFunction(Function &F); // This transformation requires dominator info - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addRequired<DominatorTreeWrapperPass>(); AU.addPreserved<DominatorTreeWrapperPass>(); diff --git a/llvm/lib/Target/ARM64/ARM64RegisterInfo.h b/llvm/lib/Target/ARM64/ARM64RegisterInfo.h index 5743e35cfe9..7691fadbcc8 100644 --- a/llvm/lib/Target/ARM64/ARM64RegisterInfo.h +++ b/llvm/lib/Target/ARM64/ARM64RegisterInfo.h @@ -40,7 +40,7 @@ public: getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override; const uint32_t *getCallPreservedMask(CallingConv::ID) const override; - unsigned getCSRFirstUseCost() const { + unsigned getCSRFirstUseCost() const override { // The cost will be compared against BlockFrequency where entry has the // value of 1 << 14. A value of 5 will choose to spill or split really // cold path instead of using a callee-saved register. diff --git a/llvm/lib/Target/ARM64/ARM64Subtarget.h b/llvm/lib/Target/ARM64/ARM64Subtarget.h index 031068c4b86..88b9c2e7aa3 100644 --- a/llvm/lib/Target/ARM64/ARM64Subtarget.h +++ b/llvm/lib/Target/ARM64/ARM64Subtarget.h @@ -100,7 +100,8 @@ public: const char *getBZeroEntry() const; void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, - MachineInstr *end, unsigned NumRegionInstrs) const; + MachineInstr *end, + unsigned NumRegionInstrs) const override; }; } // End llvm namespace diff --git a/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp b/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp index 7e3228f0230..b7e1beb8580 100644 --- a/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp +++ b/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp @@ -104,13 +104,13 @@ public: return getTM<ARM64TargetMachine>(); } - virtual bool addPreISel(); - virtual bool addInstSelector(); - virtual bool addILPOpts(); - virtual bool addPreRegAlloc(); - virtual bool addPostRegAlloc(); - virtual bool addPreSched2(); - virtual bool addPreEmitPass(); + bool addPreISel() override; + bool addInstSelector() override; + bool addILPOpts() override; + bool addPreRegAlloc() override; + bool addPostRegAlloc() override; + bool addPreSched2() override; + bool addPreEmitPass() override; }; } // namespace diff --git a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index 71cf100daf9..0c7dd73ed3d 100644 --- a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -77,7 +77,8 @@ private: bool validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc); bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, - unsigned &ErrorInfo, bool MatchingInlineAsm); + unsigned &ErrorInfo, + bool MatchingInlineAsm) override; /// @name Auto-generated Match Functions /// { @@ -113,11 +114,12 @@ public: setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } - virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, - SMLoc NameLoc, OperandVector &Operands); - virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); - virtual bool ParseDirective(AsmToken DirectiveID); - unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); + bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, + SMLoc NameLoc, OperandVector &Operands) override; + bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + bool ParseDirective(AsmToken DirectiveID) override; + unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, + unsigned Kind) override; static bool classifySymbolRef(const MCExpr *Expr, ARM64MCExpr::VariantKind &ELFRefKind, @@ -293,9 +295,9 @@ public: } /// getStartLoc - Get the location of the first token of this operand. - SMLoc getStartLoc() const { return StartLoc; } + SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const { return EndLoc; } + SMLoc getEndLoc() const override { return EndLoc; } /// getOffsetLoc - Get the location of the offset of this memory operand. SMLoc getOffsetLoc() const { return OffsetLoc; } @@ -324,7 +326,7 @@ public: return Barrier.Val; } - unsigned getReg() const { + unsigned getReg() const override { assert(Kind == k_Register && "Invalid access!"); return Reg.RegNum; } @@ -369,7 +371,7 @@ public: return Extend.Val; } - bool isImm() const { return Kind == k_Immediate; } + bool isImm() const override { return Kind == k_Immediate; } bool isSImm9() const { if (!isImm()) return false; @@ -686,7 +688,7 @@ public: return IsKnownRegister; } - bool isReg() const { return Kind == k_Register && !Reg.isVector; } + bool isReg() const override { return Kind == k_Register && !Reg.isVector; } bool isVectorReg() const { return Kind == k_Register && Reg.isVector; } bool isVectorRegLo() const { return Kind == k_Register && Reg.isVector && @@ -723,11 +725,11 @@ public: bool isVectorIndexD() const { return Kind == k_VectorIndex && VectorIndex.Val < 2; } - bool isToken() const { return Kind == k_Token; } + bool isToken() const override { return Kind == k_Token; } bool isTokenEqual(StringRef Str) const { return Kind == k_Token && getToken() == Str; } - bool isMem() const { return Kind == k_Memory; } + bool isMem() const override { return Kind == k_Memory; } bool isSysCR() const { return Kind == k_SysCR; } bool isPrefetch() const { return Kind == k_Prefetch; } bool isShifter() const { return Kind == k_Shifter; } @@ -1594,7 +1596,7 @@ public: addMemoryWritebackIndexedOperands(Inst, N, 16); } - virtual void print(raw_ostream &OS) const; + void print(raw_ostream &OS) const override; static ARM64Operand *CreateToken(StringRef Str, bool IsSuffix, SMLoc S, MCContext &Ctx) { diff --git a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.h b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.h index f60a9f07f20..8989925f36b 100644 --- a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.h +++ b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.h @@ -29,11 +29,10 @@ public: ~ARM64Disassembler() {} /// getInstruction - See MCDisassembler. - MCDisassembler::DecodeStatus getInstruction(MCInst &instr, uint64_t &size, - const MemoryObject ®ion, - uint64_t address, - raw_ostream &vStream, - raw_ostream &cStream) const; + MCDisassembler::DecodeStatus + getInstruction(MCInst &instr, uint64_t &size, const MemoryObject ®ion, + uint64_t address, raw_ostream &vStream, + raw_ostream &cStream) const override; }; } // namespace llvm diff --git a/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h b/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h index 7f2a9fe12a0..66bf6b00bce 100644 --- a/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h +++ b/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h @@ -28,8 +28,8 @@ public: ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); - virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); - virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; + void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; + void printRegName(raw_ostream &OS, unsigned RegNo) const override; // Autogenerated by tblgen. virtual void printInstruction(const MCInst *MI, raw_ostream &O); @@ -162,11 +162,11 @@ public: ARM64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); - virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); + void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; - virtual void printInstruction(const MCInst *MI, raw_ostream &O); - virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O); - virtual StringRef getRegName(unsigned RegNo) const { + void printInstruction(const MCInst *MI, raw_ostream &O) override; + bool printAliasInstr(const MCInst *MI, raw_ostream &O) override; + StringRef getRegName(unsigned RegNo) const override { return getRegisterName(RegNo); } static const char *getRegisterName(unsigned RegNo, diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp index c9b95a2c163..73a2afdb477 100644 --- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp +++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp @@ -29,9 +29,11 @@ class ARM64AsmBackend : public MCAsmBackend { public: ARM64AsmBackend(const Target &T) : MCAsmBackend() {} - unsigned getNumFixupKinds() const { return ARM64::NumTargetFixupKinds; } + unsigned getNumFixupKinds() const override { + return ARM64::NumTargetFixupKinds; + } - const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { const static MCFixupKindInfo Infos[ARM64::NumTargetFixupKinds] = { // This table *must* be in the order that the fixup_* kinds are defined in // ARM64FixupKinds.h. @@ -63,14 +65,14 @@ public: } void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t Value, bool IsPCRel) const; + uint64_t Value, bool IsPCRel) const override; - bool mayNeedRelaxation(const MCInst &Inst) const; + bool mayNeedRelaxation(const MCInst &Inst) const override; bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, - const MCAsmLayout &Layout) const; - void relaxInstruction(const MCInst &Inst, MCInst &Res) const; - bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; + const MCAsmLayout &Layout) const override; + void relaxInstruction(const MCInst &Inst, MCInst &Res) const override; + bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; void HandleAssemblerFlag(MCAssemblerFlag Flag) {} @@ -306,12 +308,12 @@ public: DarwinARM64AsmBackend(const Target &T, const MCRegisterInfo &MRI) : ARM64AsmBackend(T), MRI(MRI) {} - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { + MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { return createARM64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64, MachO::CPU_SUBTYPE_ARM64_ALL); } - virtual bool doesSectionRequireSymbols(const MCSection &Section) const { + bool doesSectionRequireSymbols(const MCSection &Section) const override { // Any section for which the linker breaks things into atoms needs to // preserve symbols, including assembler local symbols, to identify // those atoms. These sections are: @@ -348,9 +350,8 @@ public: } /// \brief Generate the compact unwind encoding from the CFI directives. - virtual uint32_t - generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const - override { + uint32_t generateCompactUnwindEncoding( + ArrayRef<MCCFIInstruction> Instrs) const override { if (Instrs.empty()) return CU::UNWIND_ARM64_MODE_FRAMELESS; @@ -491,7 +492,7 @@ public: ELFARM64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian) : ARM64AsmBackend(T), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {} - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { + MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { return createARM64ELFObjectWriter(OS, OSABI, IsLittleEndian); } diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp index 9af21d8cee8..adbf8307972 100644 --- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp +++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64ELFStreamer.cpp @@ -62,8 +62,8 @@ public: ~ARM64ELFStreamer() {} - virtual void ChangeSection(const MCSection *Section, - const MCExpr *Subsection) { + void ChangeSection(const MCSection *Section, + const MCExpr *Subsection) override { // We have to keep track of the mapping symbol state of any sections we // use. Each one should start off as EMS_None, which is provided as the // default constructor by DenseMap::lookup. @@ -76,7 +76,8 @@ public: /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to add the appropriate mapping symbol if /// necessary. - virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { + void EmitInstruction(const MCInst &Inst, + const MCSubtargetInfo &STI) override { EmitA64MappingSymbol(); MCELFStreamer::EmitInstruction(Inst, STI); } @@ -84,7 +85,7 @@ public: /// This is one of the functions used to emit data into an ELF section, so the /// ARM64 streamer overrides it to add the appropriate mapping symbol ($d) /// if necessary. - virtual void EmitBytes(StringRef Data) { + void EmitBytes(StringRef Data) override { EmitDataMappingSymbol(); MCELFStreamer::EmitBytes(Data); } @@ -92,8 +93,8 @@ public: /// This is one of the functions used to emit data into an ELF section, so the /// ARM64 streamer overrides it to add the appropriate mapping symbol ($d) /// if necessary. - virtual void EmitValueImpl(const MCExpr *Value, unsigned Size, - const SMLoc &Loc) { + void EmitValueImpl(const MCExpr *Value, unsigned Size, + const SMLoc &Loc) override { EmitDataMappingSymbol(); MCELFStreamer::EmitValueImpl(Value, Size); } diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h index 2885a66de25..324bc39560f 100644 --- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h +++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCAsmInfo.h @@ -22,9 +22,9 @@ class StringRef; class MCStreamer; struct ARM64MCAsmInfoDarwin : public MCAsmInfoDarwin { explicit ARM64MCAsmInfoDarwin(); - virtual const MCExpr *getExprForPersonalitySymbol(const MCSymbol *Sym, - unsigned Encoding, - MCStreamer &Streamer) const; + const MCExpr * + getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, + MCStreamer &Streamer) const override; }; struct ARM64MCAsmInfoELF : public MCAsmInfo { diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp index 8910337d0d2..be831b8cf0b 100644 --- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp @@ -182,7 +182,7 @@ public: void EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, - const MCSubtargetInfo &STI) const; + const MCSubtargetInfo &STI) const override; unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const; diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h index cbff6e814df..5cce6ece9fa 100644 --- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h +++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCExpr.h @@ -142,16 +142,16 @@ public: /// (e.g. ":got:", ":lo12:"). StringRef getVariantKindName() const; - void PrintImpl(raw_ostream &OS) const; + void PrintImpl(raw_ostream &OS) const override; - void AddValueSymbols(MCAssembler *) const; + void AddValueSymbols(MCAssembler *) const override; - const MCSection *FindAssociatedSection() const; + const MCSection *FindAssociatedSection() const override; bool EvaluateAsRelocatableImpl(MCValue &Res, - const MCAsmLayout *Layout) const; + const MCAsmLayout *Layout) const override; - void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const; + void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override; static bool classof(const MCExpr *E) { return E->getKind() == MCExpr::Target; diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp index ba725069a37..1c48159bbe9 100644 --- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp +++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MachObjectWriter.cpp @@ -36,7 +36,7 @@ public: void RecordRelocation(MachObjectWriter *Writer, const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target, - uint64_t &FixedValue); + uint64_t &FixedValue) override; }; } |
