diff options
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64ISelLowering.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp b/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp index 538360cf39d..385373116de 100644 --- a/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp +++ b/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp @@ -7298,6 +7298,7 @@ static SDValue performPostLD1Combine(SDNode *N, } SDValue Addr = LD->getOperand(1); + SDValue Vector = N->getOperand(0); // Search for a use of the address operand that is an increment. for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE = Addr.getNode()->use_end(); UI != UE; ++UI) { @@ -7310,6 +7311,10 @@ static SDValue performPostLD1Combine(SDNode *N, // would create a cycle. if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User)) continue; + // Also check that add is not used in the vector operand. This would also + // create a cycle. + if (User->isPredecessorOf(Vector.getNode())) + continue; // If the increment is a constant, it must match the memory ref size. SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); @@ -7324,7 +7329,7 @@ static SDValue performPostLD1Combine(SDNode *N, SmallVector<SDValue, 8> Ops; Ops.push_back(LD->getOperand(0)); // Chain if (IsLaneOp) { - Ops.push_back(N->getOperand(0)); // The vector to be inserted + Ops.push_back(Vector); // The vector to be inserted Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector } Ops.push_back(Addr); |
