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-rw-r--r--llvm/lib/Target/ARM/ARMScheduleR52.td3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleR52.td b/llvm/lib/Target/ARM/ARMScheduleR52.td
index ca3172808d3..54c3ce035d6 100644
--- a/llvm/lib/Target/ARM/ARMScheduleR52.td
+++ b/llvm/lib/Target/ARM/ARMScheduleR52.td
@@ -25,6 +25,9 @@ def CortexR52Model : SchedMachineModel {
let LoadLatency = 1; // Optimistic, assuming no misses
let MispredictPenalty = 8; // A branch direction mispredict, including PFU
let CompleteModel = 0; // Covers instructions applicable to cortex-r52.
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
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