summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--llvm/include/llvm/Target/TargetSchedule.td6
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedA53.td3
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedExynosM3.td3
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedFalkor.td3
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedKryo.td3
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedThunderX.td3
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td3
-rw-r--r--llvm/lib/Target/ARM/ARMScheduleA57.td3
-rw-r--r--llvm/lib/Target/ARM/ARMScheduleA9.td3
-rw-r--r--llvm/lib/Target/ARM/ARMScheduleR52.td3
-rw-r--r--llvm/lib/Target/ARM/ARMScheduleSwift.td3
-rw-r--r--llvm/lib/Target/Mips/MipsScheduleGeneric.td3
-rw-r--r--llvm/lib/Target/Mips/MipsScheduleP5600.td2
-rw-r--r--llvm/lib/Target/SystemZ/SystemZScheduleZ13.td3
-rw-r--r--llvm/lib/Target/SystemZ/SystemZScheduleZ14.td3
-rw-r--r--llvm/lib/Target/SystemZ/SystemZScheduleZ196.td3
-rw-r--r--llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td3
-rw-r--r--llvm/utils/TableGen/CodeGenSchedule.cpp15
18 files changed, 67 insertions, 1 deletions
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index 8ac8da84e88..8fa9bae67ca 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -99,6 +99,12 @@ class SchedMachineModel {
// resulting from changes to the instruction definitions.
bit CompleteModel = 1;
+ // Indicates that we should do full overlap checking for multiple InstrRWs
+ // definining the same instructions within the same SchedMachineModel.
+ // FIXME: Remove when all in tree targets are clean with the full check
+ // enabled.
+ bit FullInstRWOverlapCheck = 1;
+
// A processor may only implement part of published ISA, due to either new ISA
// extensions, (e.g. Pentium 4 doesn't have AVX) or implementation
// (ARM/MIPS/PowerPC/SPARC soft float cores).
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td
index 90ebd78f4ab..1838a709f24 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA53.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td
@@ -28,6 +28,9 @@ def CortexA53Model : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
index 1902b228ec3..335c3d10cf3 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -26,6 +26,9 @@ def ExynosM3Model : SchedMachineModel {
let CompleteModel = 1; // Use the default model otherwise.
list<Predicate> UnsupportedFeatures = [HasSVE];
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
index 7277198b585..84825458e47 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
@@ -25,6 +25,9 @@ def FalkorModel : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedKryo.td b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
index ce2afd499af..68de3e077c9 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedKryo.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
@@ -29,6 +29,9 @@ def KryoModel : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
index 585688aae27..fbbd3850d0f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
@@ -27,6 +27,9 @@ def ThunderXT8XModel : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
// Modeling each pipeline with BufferSize == 0 since T8X is in-order.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
index 7bdbb9a2c6d..943e75ce4a8 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
@@ -27,6 +27,9 @@ def ThunderX2T99Model : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = [HasSVE];
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
let SchedModel = ThunderX2T99Model in {
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index b90c7452e50..63f975ba6e3 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -92,6 +92,9 @@ def CortexA57Model : SchedMachineModel {
// Enable partial & runtime unrolling.
let LoopMicroOpBufferSize = 16;
let CompleteModel = 1;
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td
index 4e72b13d94c..21ac4f74cd7 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA9.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA9.td
@@ -1898,6 +1898,9 @@ def CortexA9Model : SchedMachineModel {
// FIXME: Many vector operations were never given an itinerary. We
// haven't mapped these to the new model either.
let CompleteModel = 0;
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/ARM/ARMScheduleR52.td b/llvm/lib/Target/ARM/ARMScheduleR52.td
index ca3172808d3..54c3ce035d6 100644
--- a/llvm/lib/Target/ARM/ARMScheduleR52.td
+++ b/llvm/lib/Target/ARM/ARMScheduleR52.td
@@ -25,6 +25,9 @@ def CortexR52Model : SchedMachineModel {
let LoadLatency = 1; // Optimistic, assuming no misses
let MispredictPenalty = 8; // A branch direction mispredict, including PFU
let CompleteModel = 0; // Covers instructions applicable to cortex-r52.
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/ARM/ARMScheduleSwift.td b/llvm/lib/Target/ARM/ARMScheduleSwift.td
index b838688c6f0..026468053b6 100644
--- a/llvm/lib/Target/ARM/ARMScheduleSwift.td
+++ b/llvm/lib/Target/ARM/ARMScheduleSwift.td
@@ -44,6 +44,9 @@ def SwiftModel : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 14; // A branch direction mispredict.
let CompleteModel = 0; // FIXME: Remove if all instructions are covered.
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
// Swift predicates.
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index 744392c320e..c58693cccb2 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -27,6 +27,9 @@ def MipsGenericModel : SchedMachineModel {
let CompleteModel = 1;
let PostRAScheduler = 1;
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
let SchedModel = MipsGenericModel in {
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index 556ef9ca295..1466de69d4b 100644
--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@@ -20,6 +20,8 @@ def MipsP5600Model : SchedMachineModel {
InMicroMips, InMips16Mode,
HasDSP, HasDSPR2, HasMT];
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
let SchedModel = MipsP5600Model in {
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index 72543c1eaee..ab835f634e6 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -24,6 +24,9 @@ def Z13Model : SchedMachineModel {
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 20;
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
let SchedModel = Z13Model in {
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index 698eb5627d1..e60e5583b50 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -24,6 +24,9 @@ def Z14Model : SchedMachineModel {
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 20;
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
let SchedModel = Z14Model in {
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index 4d986e8391c..43d18aa54a5 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -24,6 +24,9 @@ def Z196Model : SchedMachineModel {
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 16;
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
let SchedModel = Z196Model in {
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index a0f2115eb9d..c7f9a6e7cb6 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -24,6 +24,9 @@ def ZEC12Model : SchedMachineModel {
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 16;
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
}
let SchedModel = ZEC12Model in {
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 59ea54f1d57..c4ec4933cb8 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -781,9 +781,22 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
if (OrigNumInstrs == InstDefs.size()) {
assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
"expected a generic SchedClass");
+ Record *RWModelDef = InstRWDef->getValueAsDef("SchedModel");
+ // Make sure we didn't already have a InstRW containing this
+ // instruction on this model.
+ for (Record *RWD : RWDefs) {
+ if (RWD->getValueAsDef("SchedModel") == RWModelDef &&
+ RWModelDef->getValueAsBit("FullInstRWOverlapCheck")) {
+ for (Record *Inst : InstDefs) {
+ PrintFatalError(InstRWDef->getLoc(), "Overlapping InstRW def " +
+ Inst->getName() + " also matches " +
+ RWD->getValue("Instrs")->getValue()->getAsString());
+ }
+ }
+ }
DEBUG(dbgs() << "InstRW: Reuse SC " << OldSCIdx << ":"
<< SchedClasses[OldSCIdx].Name << " on "
- << InstRWDef->getValueAsDef("SchedModel")->getName() << "\n");
+ << RWModelDef->getName() << "\n");
SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef);
continue;
}
OpenPOWER on IntegriCloud