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-rw-r--r--llvm/lib/Target/ARM/ARM.td7
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 2c3587e6d1a..7b551c40408 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -330,6 +330,10 @@ def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
"DisablePostRAScheduler", "true",
"Don't schedule again after register allocation">;
+// Enable use of alias analysis during code generation
+def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
+ "Use alias analysis during codegen">;
+
//===----------------------------------------------------------------------===//
// ARM architecture class
//
@@ -1006,7 +1010,8 @@ def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
FeatureUseMISched,
- FeatureFPAO]>;
+ FeatureFPAO,
+ FeatureUseAA]>;
//===----------------------------------------------------------------------===//
// Register File Description
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