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path: root/llvm/lib/Target/ARM/ARM.td
Commit message (Expand)AuthorAgeFilesLines
* [ARM] Use isFMAFasterThanFMulAndFAdd for scalars as well as MVE vectorsDavid Green2020-01-051-0/+17
* Revert "[ARM] Allocatable Global Register Variables for ARM"Carey Williams2019-11-291-5/+3
* [ARM] Allocatable Global Register Variables for ARMAnna Welker2019-11-181-3/+5
* [ARM] Always enable UseAA in the arm backendDavid Green2019-11-051-12/+1
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-2/+0
* [ARM] VFPv2 only supports 16 D registers.Eli Friedman2019-09-171-7/+17
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-1/+1
* [ARM] Add MVE beats vector cost modelDavid Green2019-08-131-0/+9
* [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1Pablo Barrio2019-07-251-0/+7
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-111-1/+8
* Revert rL362953 and its followup rL362955.Simon Tatham2019-06-101-8/+1
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-101-1/+8
* [ARM] add target arch definitions for 8.1-M and MVESjoerd Meijer2019-05-301-0/+24
* [ARM] Introduce separate features for FP registersSjoerd Meijer2019-05-301-3/+22
* [ARM] Split predicates out into their own .td fileSjoerd Meijer2019-05-291-0/+1
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-39/+47
* [ARM] Cortex-M4 scheduleDavid Green2019-05-151-5/+15
* [AArch64, ARM] Add support for Exynos M5Evandro Menezes2019-03-221-0/+3
* [ARM] Add Cortex-M35PLuke Cheeseman2019-02-261-0/+10
* [AArch64] Add support for Cortex-A76 and Cortex-A76AELuke Cheeseman2019-02-251-0/+18
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM] Fix typoEvandro Menezes2019-01-121-1/+0
* [AArch64] Create feature set for Exynos M4Evandro Menezes2019-01-111-0/+3
* [ARM] Add command-line option for SBDiogo N. Sampaio2019-01-031-3/+3
* [ARM] Use Cortex-A57 sched model for Cortex-A72Sam Parker2018-10-251-1/+1
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-271-1/+6
* [ARM/AArch64][v8.5A] Add Armv8.5-A targetOliver Stannard2018-09-261-0/+18
* [ARM] Adjust the feature set for ExynosEvandro Menezes2018-09-241-0/+2
* [ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33Sjoerd Meijer2018-09-241-0/+2
* [ARM] Refactor Exynos feature set (NFC)Evandro Menezes2018-09-191-69/+21
* ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4.Tim Northover2018-09-131-0/+6
* [ARM] Adjust the feature set for ExynosEvandro Menezes2018-08-301-0/+4
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-171-0/+5
* [ARM] Adjust the feature set for ExynosEvandro Menezes2018-08-091-0/+36
* [ARM] Replace processor check with featureEvandro Menezes2018-08-091-0/+9
* [ARM] Add new target feature to fuse literal generationEvandro Menezes2018-07-271-0/+4
* [ARM] Add new feature to enable optimizing the VFP registersEvandro Menezes2018-07-201-0/+8
* [ARM][AArch64] Armv8.4-A EnablementSjoerd Meijer2018-06-291-1/+25
* Recommit of r335326, with the test fixed that I missed.Sjoerd Meijer2018-06-221-3/+6
* Reverting r335326 while I look at the test failureSjoerd Meijer2018-06-221-6/+3
* [ARM] ARMv6m and v8m.baseline strict alignSjoerd Meijer2018-06-221-3/+6
* [ARM] Enable useAA() for the in-order Cortex-R52David Green2018-06-211-1/+6
* [AArch64, ARM] Add support for Samsung Exynos M4Evandro Menezes2018-06-061-0/+6
* [ARM] Enable misched for R52.David Green2018-04-271-0/+1
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
* [ARM] Fix erroneous availability of SMMLS for Armv7-MAndre Vieira2018-01-121-1/+2
* [ARM] Armv8-R DFB instructionSam Parker2017-12-211-0/+4
* [ARM] Use new assembler diags for ARMOliver Stannard2017-10-031-0/+5
* [ARM] Reverse PostRASched subtarget feature logicSam Parker2017-08-311-12/+11
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-211-0/+14
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