diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
68 files changed, 220 insertions, 220 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h index 51d48a0c732..3c7e8dd764c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief AMDGPU Assembly printer class. +/// AMDGPU Assembly printer class. // //===----------------------------------------------------------------------===// @@ -135,7 +135,7 @@ private: const MachineFunction &MF, const SIProgramInfo &ProgramInfo) const; - /// \brief Emit register usage information so that the GPU driver + /// Emit register usage information so that the GPU driver /// can correctly setup the GPU state. void EmitProgramInfoR600(const MachineFunction &MF); void EmitProgramInfoSI(const MachineFunction &MF, @@ -160,16 +160,16 @@ public: bool doFinalization(Module &M) override; bool runOnMachineFunction(MachineFunction &MF) override; - /// \brief Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated + /// Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated /// pseudo lowering. bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const; - /// \brief Lower the specified LLVM Constant to an MCExpr. + /// Lower the specified LLVM Constant to an MCExpr. /// The AsmPrinter::lowerConstantof does not know how to lower /// addrspacecast, therefore they should be lowered by this function. const MCExpr *lowerConstant(const Constant *CV) override; - /// \brief tblgen'erated driver function for lowering simple MI->MC pseudo + /// tblgen'erated driver function for lowering simple MI->MC pseudo /// instructions. bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index 0c30f051932..b1ae1e0cb08 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -56,7 +56,7 @@ class AMDGPUCodeGenPrepare : public FunctionPass, bool HasUnsafeFPMath = false; AMDGPUAS AMDGPUASI; - /// \brief Copies exact/nsw/nuw flags (if any) from binary operation \p I to + /// Copies exact/nsw/nuw flags (if any) from binary operation \p I to /// binary operation \p V. /// /// \returns Binary operation \p V. @@ -80,7 +80,7 @@ class AMDGPUCodeGenPrepare : public FunctionPass, /// false otherwise. bool needsPromotionToI32(const Type *T) const; - /// \brief Promotes uniform binary operation \p I to equivalent 32 bit binary + /// Promotes uniform binary operation \p I to equivalent 32 bit binary /// operation. /// /// \details \p I's base element bit width must be greater than 1 and less @@ -93,7 +93,7 @@ class AMDGPUCodeGenPrepare : public FunctionPass, /// false otherwise. bool promoteUniformOpToI32(BinaryOperator &I) const; - /// \brief Promotes uniform 'icmp' operation \p I to 32 bit 'icmp' operation. + /// Promotes uniform 'icmp' operation \p I to 32 bit 'icmp' operation. /// /// \details \p I's base element bit width must be greater than 1 and less /// than or equal 16. Promotion is done by sign or zero extending operands to @@ -102,7 +102,7 @@ class AMDGPUCodeGenPrepare : public FunctionPass, /// \returns True. bool promoteUniformOpToI32(ICmpInst &I) const; - /// \brief Promotes uniform 'select' operation \p I to 32 bit 'select' + /// Promotes uniform 'select' operation \p I to 32 bit 'select' /// operation. /// /// \details \p I's base element bit width must be greater than 1 and less @@ -113,7 +113,7 @@ class AMDGPUCodeGenPrepare : public FunctionPass, /// \returns True. bool promoteUniformOpToI32(SelectInst &I) const; - /// \brief Promotes uniform 'bitreverse' intrinsic \p I to 32 bit 'bitreverse' + /// Promotes uniform 'bitreverse' intrinsic \p I to 32 bit 'bitreverse' /// intrinsic. /// /// \details \p I's base element bit width must be greater than 1 and less @@ -125,7 +125,7 @@ class AMDGPUCodeGenPrepare : public FunctionPass, /// /// \returns True. bool promoteUniformBitreverseToI32(IntrinsicInst &I) const; - /// \brief Widen a scalar load. + /// Widen a scalar load. /// /// \details \p Widen scalar load for uniform, small type loads from constant // memory / to a full 32-bits and then truncate the input to allow a scalar diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h index 91fe921bfee..ee836bf8a63 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Interface to describe a layout of a stack frame on an AMDGPU target. +/// Interface to describe a layout of a stack frame on an AMDGPU target. // //===----------------------------------------------------------------------===// @@ -19,7 +19,7 @@ namespace llvm { -/// \brief Information about the stack frame layout on the AMDGPU targets. +/// Information about the stack frame layout on the AMDGPU targets. /// /// It holds the direction of the stack growth, the known stack alignment on /// entry to each function, and the offset to the locals area. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 47321a76e5c..16fb438de01 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -8,7 +8,7 @@ //==-----------------------------------------------------------------------===// // /// \file -/// \brief Defines an instruction selector for the AMDGPU target. +/// Defines an instruction selector for the AMDGPU target. // //===----------------------------------------------------------------------===// @@ -244,14 +244,14 @@ INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo) INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "isel", "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) -/// \brief This pass converts a legalized DAG into a AMDGPU-specific +/// This pass converts a legalized DAG into a AMDGPU-specific // DAG, ready for instruction scheduling. FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel) { return new AMDGPUDAGToDAGISel(TM, OptLevel); } -/// \brief This pass converts a legalized DAG into a R600-specific +/// This pass converts a legalized DAG into a R600-specific // DAG, ready for instruction scheduling. FunctionPass *llvm::createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel) { @@ -287,7 +287,7 @@ bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const { return false; } -/// \brief Determine the register class for \p OpNo +/// Determine the register class for \p OpNo /// \returns The register class of the virtual register that will be used for /// the given operand number \OpNo or NULL if the register class cannot be /// determined. diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index c60e25390c1..fffcb2fb566 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief This is the parent TargetLowering class for hardware code gen +/// This is the parent TargetLowering class for hardware code gen /// targets. // //===----------------------------------------------------------------------===// @@ -1321,7 +1321,7 @@ SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args); } -/// \brief Generate Min/Max node +/// Generate Min/Max node SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index 94b5332ff6a..857a69a1951 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Interface definition of the TargetLowering class that is common +/// Interface definition of the TargetLowering class that is common /// to all AMD GPUs. // //===----------------------------------------------------------------------===// @@ -44,7 +44,7 @@ protected: SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; - /// \brief Split a vector store into multiple scalar stores. + /// Split a vector store into multiple scalar stores. /// \returns The resulting chain. SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const; @@ -108,10 +108,10 @@ protected: SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const; SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const; - /// \brief Split a vector load into 2 loads of half the vector. + /// Split a vector load into 2 loads of half the vector. SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const; - /// \brief Split a vector store into 2 stores of half the vector. + /// Split a vector store into 2 stores of half the vector. SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; @@ -227,7 +227,7 @@ public: virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const = 0; - /// \brief Determine which of the bits specified in \p Mask are known to be + /// Determine which of the bits specified in \p Mask are known to be /// either zero or one and return them in the \p KnownZero and \p KnownOne /// bitsets. void computeKnownBitsForTargetNode(const SDValue Op, @@ -240,7 +240,7 @@ public: const SelectionDAG &DAG, unsigned Depth = 0) const override; - /// \brief Helper function that adds Reg to the LiveIn list of the DAG's + /// Helper function that adds Reg to the LiveIn list of the DAG's /// MachineFunction. /// /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise @@ -288,7 +288,7 @@ public: GRID_OFFSET, }; - /// \brief Helper function that returns the byte offset of the given + /// Helper function that returns the byte offset of the given /// type of implicit parameter. uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInline.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInline.cpp index ff9e7b50ed5..ca77795ce10 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInline.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInline.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief This is AMDGPU specific replacement of the standard inliner. +/// This is AMDGPU specific replacement of the standard inliner. /// The main purpose is to account for the fact that calls not only expensive /// on the AMDGPU, but much more expensive if a private memory pointer is /// passed to a function as an argument. In this situation, we are unable to diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp index 32118df5382..0b173abf035 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Implementation of the TargetInstrInfo class that is common to all +/// Implementation of the TargetInstrInfo class that is common to all /// AMD GPUs. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h index 766ee3d6f1c..a1ea3ff2bf8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Contains the definition of a TargetInstrInfo class that is common +/// Contains the definition of a TargetInstrInfo class that is common /// to all AMD GPUs. // //===----------------------------------------------------------------------===// @@ -46,7 +46,7 @@ public: int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override; - /// \brief Return a target-specific opcode if Opcode is a pseudo instruction. + /// Return a target-specific opcode if Opcode is a pseudo instruction. /// Return -1 if the target-specific opcode for the pseudo instruction does /// not exist. If Opcode is not a pseudo instruction, this is identity. int pseudoToMCOpcode(int Opcode) const; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp index 86dc9bd9ea7..84b6c5b91b7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp @@ -8,7 +8,7 @@ //==-----------------------------------------------------------------------===// // /// \file -/// \brief AMDGPU Implementation of the IntrinsicInfo class. +/// AMDGPU Implementation of the IntrinsicInfo class. // //===-----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h index 6cb8b964464..adbd7045ab9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h @@ -8,7 +8,7 @@ //==-----------------------------------------------------------------------===// // /// \file -/// \brief Interface for the AMDGPU Implementation of the Intrinsic Info class. +/// Interface for the AMDGPU Implementation of the Intrinsic Info class. // //===-----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINTRINSICINFO_H diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp index f594767c8ed..dd45ced6ecc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief This file does AMD library function optimizations. +/// This file does AMD library function optimizations. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp index 23fd8113932..9826579565f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst. +/// Code to lower AMDGPU MachineInstrs to their corresponding MCInst. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h index 57d2d85daec..ea70e636b30 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h @@ -36,7 +36,7 @@ public: bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const; - /// \brief Lower a MachineInstr to an MCInst + /// Lower a MachineInstr to an MCInst void lower(const MachineInstr *MI, MCInst &OutMI) const; }; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp index 3164140abe2..7b9f673c418 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief AMDGPU Machine Module Info. +/// AMDGPU Machine Module Info. /// // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h index 1a728c6bd04..1219ab26fb6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief AMDGPU Machine Module Info. +/// AMDGPU Machine Module Info. /// // //===----------------------------------------------------------------------===// @@ -30,14 +30,14 @@ private: // All supported memory/synchronization scopes can be found here: // http://llvm.org/docs/AMDGPUUsage.html#memory-scopes - /// \brief Agent synchronization scope ID. + /// Agent synchronization scope ID. SyncScope::ID AgentSSID; - /// \brief Workgroup synchronization scope ID. + /// Workgroup synchronization scope ID. SyncScope::ID WorkgroupSSID; - /// \brief Wavefront synchronization scope ID. + /// Wavefront synchronization scope ID. SyncScope::ID WavefrontSSID; - /// \brief In AMDGPU target synchronization scopes are inclusive, meaning a + /// In AMDGPU target synchronization scopes are inclusive, meaning a /// larger synchronization scope is inclusive of a smaller synchronization /// scope. /// @@ -74,7 +74,7 @@ public: return WavefrontSSID; } - /// \brief In AMDGPU target synchronization scopes are inclusive, meaning a + /// In AMDGPU target synchronization scopes are inclusive, meaning a /// larger synchronization scope is inclusive of a smaller synchronization /// scope. /// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp index 7263ba73d15..4c4e428008d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp @@ -22,7 +22,7 @@ using namespace llvm; namespace { -/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused +/// Check if the instr pair, FirstMI and SecondMI, should be fused /// together. Given SecondMI, when FirstMI is unspecified, then check if /// SecondMI may be part of a fused pair at all. static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp index 514670af2d0..265104a8643 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // // \file -// \brief This post-linking pass replaces the function pointer of enqueued +// This post-linking pass replaces the function pointer of enqueued // block kernel with a global variable (runtime handle) and adds // "runtime-handle" attribute to the enqueued block kernel. // @@ -50,7 +50,7 @@ using namespace llvm; namespace { -/// \brief Lower enqueued blocks. +/// Lower enqueued blocks. class AMDGPUOpenCLEnqueuedBlockLowering : public ModulePass { public: static char ID; diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp index 242b97b1090..df9b4c2c145 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Parent TargetRegisterInfo class common to all hw codegen targets. +/// Parent TargetRegisterInfo class common to all hw codegen targets. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h index eb07ad69292..d8ef601371f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief TargetRegisterInfo interface that is implemented by all hw codegen +/// TargetRegisterInfo interface that is implemented by all hw codegen /// targets. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index b3b485e548b..40c583ba4f5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Implements the AMDGPU specific subclass of TargetSubtarget. +/// Implements the AMDGPU specific subclass of TargetSubtarget. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h index 996ae9c2f0b..1347427da34 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -8,7 +8,7 @@ //==-----------------------------------------------------------------------===// // /// \file -/// \brief AMDGPU specific subclass of TargetSubtarget. +/// AMDGPU specific subclass of TargetSubtarget. // //===----------------------------------------------------------------------===// @@ -547,7 +547,7 @@ public: return HasDLInsts; } - /// \brief Returns the offset in bytes from the start of the input buffer + /// Returns the offset in bytes from the start of the input buffer /// of the first explicit kernel argument. unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const { return isAmdCodeObjectV2(MF) ? 0 : 36; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index e4cd22c61ea..60e26fa72f7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief The AMDGPU target machine contains all of the hardware specific +/// The AMDGPU target machine contains all of the hardware specific /// information needed to emit code for R600 and SI GPUs. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index 5f9b2a7fca2..56ed10e0625 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief The AMDGPU TargetMachine interface definition for hw codgen targets. +/// The AMDGPU TargetMachine interface definition for hw codgen targets. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.h index ca6210f6929..dd9dc1a88fc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// /// /// \file -/// \brief This file declares the AMDGPU-specific subclass of +/// This file declares the AMDGPU-specific subclass of /// TargetLoweringObjectFile. /// //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp b/llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp index b78568e89cf..1f6d9234c1e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // // \file -// \brief This pass that unifies multiple OpenCL metadata due to linking. +// This pass that unifies multiple OpenCL metadata due to linking. // //===----------------------------------------------------------------------===// @@ -37,7 +37,7 @@ namespace { } // end namespace kOCLMD - /// \brief Unify multiple OpenCL metadata due to linking. + /// Unify multiple OpenCL metadata due to linking. class AMDGPUUnifyMetadata : public ModulePass { public: static char ID; @@ -47,7 +47,7 @@ namespace { private: bool runOnModule(Module &M) override; - /// \brief Unify version metadata. + /// Unify version metadata. /// \return true if changes are made. /// Assume the named metadata has operands each of which is a pair of /// integer constant, e.g. @@ -82,7 +82,7 @@ namespace { return true; } - /// \brief Unify version metadata. + /// Unify version metadata. /// \return true if changes are made. /// Assume the named metadata has operands each of which is a list e.g. /// !Name = {!n1, !n2} diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUHSAMetadataStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUHSAMetadataStreamer.cpp index 3b9561327ae..402324fe6a7 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUHSAMetadataStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUHSAMetadataStreamer.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief AMDGPU HSA Metadata Streamer. +/// AMDGPU HSA Metadata Streamer. /// // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUHSAMetadataStreamer.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUHSAMetadataStreamer.h index bd6515521a7..dfbb5d3ccee 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUHSAMetadataStreamer.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUHSAMetadataStreamer.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief AMDGPU HSA Metadata Streamer. +/// AMDGPU HSA Metadata Streamer. /// // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp index 521b3b39bba..cae7a7a6c7e 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief CodeEmitter interface for R600 and SI codegen. +/// CodeEmitter interface for R600 and SI codegen. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h index 1b062064ace..dcc10a032af 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief CodeEmitter interface for R600 and SI codegen. +/// CodeEmitter interface for R600 and SI codegen. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp index 7e581204be1..08ecb5f101a 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief This file provides AMDGPU specific target descriptions. +/// This file provides AMDGPU specific target descriptions. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h index 1173dfd437c..316b119372c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Provides AMDGPU specific target descriptions. +/// Provides AMDGPU specific target descriptions. // //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp index eab90e1d344..0d471b1f5ce 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp @@ -9,7 +9,7 @@ // /// \file /// -/// \brief The R600 code emitter produces machine code that can be executed +/// The R600 code emitter produces machine code that can be executed /// directly on the GPU device. // //===----------------------------------------------------------------------===// @@ -45,7 +45,7 @@ public: R600MCCodeEmitter(const R600MCCodeEmitter &) = delete; R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete; - /// \brief Encode the instruction and write it to the OS. + /// Encode the instruction and write it to the OS. void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const override; diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index 0d917a192fd..e3e23d73f41 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief The SI code emitter produces machine code that can be executed +/// The SI code emitter produces machine code that can be executed /// directly on the GPU device. // //===----------------------------------------------------------------------===// @@ -43,7 +43,7 @@ namespace { class SIMCCodeEmitter : public AMDGPUMCCodeEmitter { const MCRegisterInfo &MRI; - /// \brief Encode an fp or int literal + /// Encode an fp or int literal uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo, const MCSubtargetInfo &STI) const; @@ -54,7 +54,7 @@ public: SIMCCodeEmitter(const SIMCCodeEmitter &) = delete; SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete; - /// \brief Encode the instruction and write it to the OS. + /// Encode the instruction and write it to the OS. void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const override; @@ -64,7 +64,7 @@ public: SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const override; - /// \brief Use a fixup to encode the simm16 field for SOPP branch + /// Use a fixup to encode the simm16 field for SOPP branch /// instructions. unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, diff --git a/llvm/lib/Target/AMDGPU/R600Defines.h b/llvm/lib/Target/AMDGPU/R600Defines.h index 534461adc59..0d33d82e8e0 100644 --- a/llvm/lib/Target/AMDGPU/R600Defines.h +++ b/llvm/lib/Target/AMDGPU/R600Defines.h @@ -23,7 +23,7 @@ #define MO_FLAG_LAST (1 << 6) #define NUM_MO_FLAGS 7 -/// \brief Helper for getting the operand index for the instruction flags +/// Helper for getting the operand index for the instruction flags /// operand. #define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3) @@ -52,7 +52,7 @@ namespace R600_InstFlag { #define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS) -/// \brief Defines for extracting register information from register encoding +/// Defines for extracting register information from register encoding #define HW_REG_MASK 0x1ff #define HW_CHAN_SHIFT 9 diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index be37dbf57b1..11423a629e7 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Custom DAG lowering for R600 +/// Custom DAG lowering for R600 // //===----------------------------------------------------------------------===// @@ -2116,7 +2116,7 @@ bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, } } -/// \brief Fold the instructions after selecting them +/// Fold the instructions after selecting them SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, SelectionDAG &DAG) const { const R600InstrInfo *TII = getSubtarget()->getInstrInfo(); diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.h b/llvm/lib/Target/AMDGPU/R600ISelLowering.h index 2a774693f02..cc55a414139 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.h +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief R600 DAG Lowering interface definition +/// R600 DAG Lowering interface definition // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 3e718f14c7f..9b8cca123b8 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief R600 Implementation of TargetInstrInfo. +/// R600 Implementation of TargetInstrInfo. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h index 9999cc516f6..0af17d01c94 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Interface definition for R600InstrInfo +/// Interface definition for R600InstrInfo // //===----------------------------------------------------------------------===// @@ -150,7 +150,7 @@ public: /// Same but using const index set instead of MI set. bool fitsConstReadLimitations(const std::vector<unsigned>&) const; - /// \brief Vector instructions are instructions that must fill all + /// Vector instructions are instructions that must fill all /// instruction slots within an instruction group. bool isVector(const MachineInstr &MI) const; @@ -209,7 +209,7 @@ public: bool expandPostRAPseudo(MachineInstr &MI) const override; - /// \brief Reserve the registers that may be accesed using indirect addressing. + /// Reserve the registers that may be accesed using indirect addressing. void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const; @@ -236,7 +236,7 @@ public: /// read or write or -1 if indirect addressing is not used by this program. int getIndirectIndexEnd(const MachineFunction &MF) const; - /// \brief Build instruction(s) for an indirect register write. + /// Build instruction(s) for an indirect register write. /// /// \returns The instruction that performs the indirect register write MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, @@ -244,7 +244,7 @@ public: unsigned ValueReg, unsigned Address, unsigned OffsetReg) const; - /// \brief Build instruction(s) for an indirect register read. + /// Build instruction(s) for an indirect register read. /// /// \returns The instruction that performs the indirect register read MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, @@ -282,23 +282,23 @@ public: MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const; - /// \brief Get the index of Op in the MachineInstr. + /// Get the index of Op in the MachineInstr. /// /// \returns -1 if the Instruction does not contain the specified \p Op. int getOperandIdx(const MachineInstr &MI, unsigned Op) const; - /// \brief Get the index of \p Op for the given Opcode. + /// Get the index of \p Op for the given Opcode. /// /// \returns -1 if the Instruction does not contain the specified \p Op. int getOperandIdx(unsigned Opcode, unsigned Op) const; - /// \brief Helper function for setting instruction flag values. + /// Helper function for setting instruction flag values. void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const; - ///\brief Add one of the MO_FLAG* flags to the specified \p Operand. + ///Add one of the MO_FLAG* flags to the specified \p Operand. void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const; - ///\brief Determine if the specified \p Flag is set on this \p Operand. + ///Determine if the specified \p Flag is set on this \p Operand. bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const; /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2) @@ -308,7 +308,7 @@ public: MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0, unsigned Flag = 0) const; - /// \brief Clear the specified flag on the instruction. + /// Clear the specified flag on the instruction. void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const; // Helper functions that check the opcode for status information diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp index a7e540f9d14..f8d062ef52d 100644 --- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief R600 Machine Scheduler interface +/// R600 Machine Scheduler interface // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.h b/llvm/lib/Target/AMDGPU/R600MachineScheduler.h index 9a677057047..8a9a8d3d1e2 100644 --- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.h +++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief R600 Machine Scheduler interface +/// R600 Machine Scheduler interface // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp index b622110690c..9544ee75089 100644 --- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief R600 implementation of the TargetRegisterInfo class. +/// R600 implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.h b/llvm/lib/Target/AMDGPU/R600RegisterInfo.h index f0d9644b02f..305878522dd 100644 --- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Interface definition for R600RegisterInfo +/// Interface definition for R600RegisterInfo // //===----------------------------------------------------------------------===// @@ -30,12 +30,12 @@ struct R600RegisterInfo final : public AMDGPURegisterInfo { const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; unsigned getFrameRegister(const MachineFunction &MF) const override; - /// \brief get the HW encoding for a register's channel. + /// get the HW encoding for a register's channel. unsigned getHWRegChan(unsigned reg) const; unsigned getHWRegIndex(unsigned Reg) const; - /// \brief get the register class of the specified type to use in the + /// get the register class of the specified type to use in the /// CFGStructurizer const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const; diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp index 68561ac38cd..11fea5d6ee7 100644 --- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp @@ -133,7 +133,7 @@ INITIALIZE_PASS_END(SIAnnotateControlFlow, DEBUG_TYPE, char SIAnnotateControlFlow::ID = 0; -/// \brief Initialize all the types and constants used in the pass +/// Initialize all the types and constants used in the pass bool SIAnnotateControlFlow::doInitialization(Module &M) { LLVMContext &Context = M.getContext(); @@ -157,29 +157,29 @@ bool SIAnnotateControlFlow::doInitialization(Module &M) { return false; } -/// \brief Is the branch condition uniform or did the StructurizeCFG pass +/// Is the branch condition uniform or did the StructurizeCFG pass /// consider it as such? bool SIAnnotateControlFlow::isUniform(BranchInst *T) { return DA->isUniform(T->getCondition()) || T->getMetadata("structurizecfg.uniform") != nullptr; } -/// \brief Is BB the last block saved on the stack ? +/// Is BB the last block saved on the stack ? bool SIAnnotateControlFlow::isTopOfStack(BasicBlock *BB) { return !Stack.empty() && Stack.back().first == BB; } -/// \brief Pop the last saved value from the control flow stack +/// Pop the last saved value from the control flow stack Value *SIAnnotateControlFlow::popSaved() { return Stack.pop_back_val().second; } -/// \brief Push a BB and saved value to the control flow stack +/// Push a BB and saved value to the control flow stack void SIAnnotateControlFlow::push(BasicBlock *BB, Value *Saved) { Stack.push_back(std::make_pair(BB, Saved)); } -/// \brief Can the condition represented by this PHI node treated like +/// Can the condition represented by this PHI node treated like /// an "Else" block? bool SIAnnotateControlFlow::isElse(PHINode *Phi) { BasicBlock *IDom = DT->getNode(Phi->getParent())->getIDom()->getBlock(); @@ -198,14 +198,14 @@ bool SIAnnotateControlFlow::isElse(PHINode *Phi) { return true; } -// \brief Erase "Phi" if it is not used any more +// Erase "Phi" if it is not used any more void SIAnnotateControlFlow::eraseIfUnused(PHINode *Phi) { if (RecursivelyDeleteDeadPHINode(Phi)) { DEBUG(dbgs() << "Erased unused condition phi\n"); } } -/// \brief Open a new "If" block +/// Open a new "If" block void SIAnnotateControlFlow::openIf(BranchInst *Term) { if (isUniform(Term)) return; @@ -215,7 +215,7 @@ void SIAnnotateControlFlow::openIf(BranchInst *Term) { push(Term->getSuccessor(1), ExtractValueInst::Create(Ret, 1, "", Term)); } -/// \brief Close the last "If" block and open a new "Else" block +/// Close the last "If" block and open a new "Else" block void SIAnnotateControlFlow::insertElse(BranchInst *Term) { if (isUniform(Term)) { return; @@ -225,7 +225,7 @@ void SIAnnotateControlFlow::insertElse(BranchInst *Term) { push(Term->getSuccessor(1), ExtractValueInst::Create(Ret, 1, "", Term)); } -/// \brief Recursively handle the condition leading to a loop +/// Recursively handle the condition leading to a loop Value *SIAnnotateControlFlow::handleLoopCondition( Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term, SmallVectorImpl<WeakTrackingVH> &LoopPhiConditions) { @@ -322,7 +322,7 @@ Value *SIAnnotateControlFlow::handleLoopCondition( llvm_unreachable("Unhandled loop condition!"); } -/// \brief Handle a back edge (loop) +/// Handle a back edge (loop) void SIAnnotateControlFlow::handleLoop(BranchInst *Term) { if (isUniform(Term)) return; @@ -353,7 +353,7 @@ void SIAnnotateControlFlow::handleLoop(BranchInst *Term) { push(Term->getSuccessor(0), Arg); } -/// \brief Close the last opened control flow +/// Close the last opened control flow void SIAnnotateControlFlow::closeControlFlow(BasicBlock *BB) { llvm::Loop *L = LI->getLoopFor(BB); @@ -381,7 +381,7 @@ void SIAnnotateControlFlow::closeControlFlow(BasicBlock *BB) { CallInst::Create(EndCf, Exec, "", FirstInsertionPt); } -/// \brief Annotate the control flow with intrinsics so the backend can +/// Annotate the control flow with intrinsics so the backend can /// recognize if/then/else and loops. bool SIAnnotateControlFlow::runOnFunction(Function &F) { DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree(); @@ -430,7 +430,7 @@ bool SIAnnotateControlFlow::runOnFunction(Function &F) { return true; } -/// \brief Create the annotation pass +/// Create the annotation pass FunctionPass *llvm::createSIAnnotateControlFlowPass() { return new SIAnnotateControlFlow(); } diff --git a/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp b/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp index b5c439b21b8..69ec3816772 100644 --- a/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp +++ b/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Inserts one nop instruction for each high level source statement for +/// Inserts one nop instruction for each high level source statement for /// debugger usage. /// /// Tools, such as a debugger, need to pause execution based on user input (i.e. diff --git a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp index 3d3121788b5..7a3caf4db71 100644 --- a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Add implicit use of exec to vector register copies. +/// Add implicit use of exec to vector register copies. /// //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp b/llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp index 3493c7775f0..666335531e7 100644 --- a/llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Computations in WWM can overwrite values in inactive channels for +/// Computations in WWM can overwrite values in inactive channels for /// variables that the register allocator thinks are dead. This pass adds fake /// uses of those variables to WWM instructions to make sure that they aren't /// overwritten. diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.h b/llvm/lib/Target/AMDGPU/SIFrameLowering.h index df6f1632a31..6be7f262208 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.h +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.h @@ -66,7 +66,7 @@ private: SIMachineFunctionInfo *MFI, MachineFunction &MF) const; - /// \brief Emits debugger prologue. + /// Emits debugger prologue. void emitDebuggerPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const; // Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set. diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index ebc686ca83d..4186e221ede 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Custom DAG lowering for SI +/// Custom DAG lowering for SI // //===----------------------------------------------------------------------===// @@ -3785,7 +3785,7 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N, } } -/// \brief Helper function for LowerBRCOND +/// Helper function for LowerBRCOND static SDNode *findUser(SDValue Value, unsigned Opcode) { SDNode *Parent = Value.getNode(); @@ -7129,7 +7129,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); } -/// \brief Helper function for adjustWritemask +/// Helper function for adjustWritemask static unsigned SubIdx2Lane(unsigned Idx) { switch (Idx) { default: return 0; @@ -7140,7 +7140,7 @@ static unsigned SubIdx2Lane(unsigned Idx) { } } -/// \brief Adjust the writemask of MIMG instructions +/// Adjust the writemask of MIMG instructions SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node, SelectionDAG &DAG) const { SDNode *Users[4] = { nullptr }; @@ -7262,7 +7262,7 @@ static bool isFrameIndexOp(SDValue Op) { return isa<FrameIndexSDNode>(Op); } -/// \brief Legalize target independent instructions (e.g. INSERT_SUBREG) +/// Legalize target independent instructions (e.g. INSERT_SUBREG) /// with frame index operands. /// LLVM assumes that inputs are to these instructions are registers. SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node, @@ -7309,7 +7309,7 @@ SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node, return DAG.UpdateNodeOperands(Node, Ops); } -/// \brief Fold the instructions after selecting them. +/// Fold the instructions after selecting them. /// Returns null if users were already updated. SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node, SelectionDAG &DAG) const { @@ -7383,7 +7383,7 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node, return Node; } -/// \brief Assign the register class depending on the number of +/// Assign the register class depending on the number of /// bits set in the writemask void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const { @@ -7470,7 +7470,7 @@ MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG, return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1); } -/// \brief Return a resource descriptor with the 'Add TID' bit enabled +/// Return a resource descriptor with the 'Add TID' bit enabled /// The TID (Thread ID) is multiplied by the stride value (bits [61:48] /// of the resource descriptor) to create an offset, which is added to /// the resource pointer. diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index 2c6e61d316d..fba383dbe4c 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief SI DAG Lowering interface definition +/// SI DAG Lowering interface definition // //===----------------------------------------------------------------------===// @@ -64,7 +64,7 @@ class SITargetLowering final : public AMDGPUTargetLowering { SelectionDAG &DAG) const; SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const; - /// \brief Converts \p Op, which must be of floating point type, to the + /// Converts \p Op, which must be of floating point type, to the /// floating point type \p VT, by either extending or truncating it. SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, SDValue Op, @@ -75,7 +75,7 @@ class SITargetLowering final : public AMDGPUTargetLowering { SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, bool Signed, const ISD::InputArg *Arg = nullptr) const; - /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16. + /// Custom lowering for ISD::FP_ROUND for MVT::f16. SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, diff --git a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp index eb7277b7a5b..37903cdd6e8 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief This pass inserts branches on the 0 exec mask over divergent branches +/// This pass inserts branches on the 0 exec mask over divergent branches /// branches when it's expected that jumping over the untaken control flow will /// be cheaper than having every workitem no-op through it. // diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 543d07347cc..2aa4297477b 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Insert wait instructions for memory reads and writes. +/// Insert wait instructions for memory reads and writes. /// /// Memory reads and writes are issued asynchronously, so we need to insert /// S_WAITCNT instructions when we want to access any of their results or @@ -843,7 +843,7 @@ static bool readsVCCZ(const MachineInstr &MI) { !MI.getOperand(1).isUndef(); } -/// \brief Given wait count encodings checks if LHS is stronger than RHS. +/// Given wait count encodings checks if LHS is stronger than RHS. bool SIInsertWaitcnts::isWaitcntStronger(unsigned LHS, unsigned RHS) { if (AMDGPU::decodeVmcnt(IV, LHS) > AMDGPU::decodeVmcnt(IV, RHS)) return false; @@ -854,7 +854,7 @@ bool SIInsertWaitcnts::isWaitcntStronger(unsigned LHS, unsigned RHS) { return true; } -/// \brief Given wait count encodings create a new encoding which is stronger +/// Given wait count encodings create a new encoding which is stronger /// or equal to both. unsigned SIInsertWaitcnts::combineWaitcnt(unsigned LHS, unsigned RHS) { unsigned VmCnt = std::min(AMDGPU::decodeVmcnt(IV, LHS), @@ -866,7 +866,7 @@ unsigned SIInsertWaitcnts::combineWaitcnt(unsigned LHS, unsigned RHS) { return AMDGPU::encodeWaitcnt(IV, VmCnt, ExpCnt, LgkmCnt); } -/// \brief Generate s_waitcnt instruction to be placed before cur_Inst. +/// Generate s_waitcnt instruction to be placed before cur_Inst. /// Instructions of a given type are returned in order, /// but instructions of different types can complete out of order. /// We rely on this in-order completion diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp index d06d96be542..65b22bde51d 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Insert wait instructions for memory reads and writes. +/// Insert wait instructions for memory reads and writes. /// /// Memory reads and writes are issued asynchronously, so we need to insert /// S_WAITCNT instructions when we want to access any of their results or @@ -49,7 +49,7 @@ using namespace llvm; namespace { -/// \brief One variable for each of the hardware counters +/// One variable for each of the hardware counters using Counters = union { struct { unsigned VM; @@ -76,32 +76,32 @@ private: const MachineRegisterInfo *MRI; AMDGPU::IsaInfo::IsaVersion ISA; - /// \brief Constant zero value + /// Constant zero value static const Counters ZeroCounts; - /// \brief Hardware limits + /// Hardware limits Counters HardwareLimits; - /// \brief Counter values we have already waited on. + /// Counter values we have already waited on. Counters WaitedOn; - /// \brief Counter values that we must wait on before the next counter + /// Counter values that we must wait on before the next counter /// increase. Counters DelayedWaitOn; - /// \brief Counter values for last instruction issued. + /// Counter values for last instruction issued. Counters LastIssued; - /// \brief Registers used by async instructions. + /// Registers used by async instructions. RegCounters UsedRegs; - /// \brief Registers defined by async instructions. + /// Registers defined by async instructions. RegCounters DefinedRegs; - /// \brief Different export instruction types seen since last wait. + /// Different export instruction types seen since last wait. unsigned ExpInstrTypesSeen = 0; - /// \brief Type of the last opcode. + /// Type of the last opcode. InstType LastOpcodeType; bool LastInstWritesM0; @@ -109,42 +109,42 @@ private: /// Whether or not we have flat operations outstanding. bool IsFlatOutstanding; - /// \brief Whether the machine function returns void + /// Whether the machine function returns void bool ReturnsVoid; /// Whether the VCCZ bit is possibly corrupt bool VCCZCorrupt = false; - /// \brief Get increment/decrement amount for this instruction. + /// Get increment/decrement amount for this instruction. Counters getHwCounts(MachineInstr &MI); - /// \brief Is operand relevant for async execution? + /// Is operand relevant for async execution? bool isOpRelevant(MachineOperand &Op); - /// \brief Get register interval an operand affects. + /// Get register interval an operand affects. RegInterval getRegInterval(const TargetRegisterClass *RC, const MachineOperand &Reg) const; - /// \brief Handle instructions async components + /// Handle instructions async components void pushInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const Counters& Increment); - /// \brief Insert the actual wait instruction + /// Insert the actual wait instruction bool insertWait(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const Counters &Counts); - /// \brief Handle existing wait instructions (from intrinsics) + /// Handle existing wait instructions (from intrinsics) void handleExistingWait(MachineBasicBlock::iterator I); - /// \brief Do we need def2def checks? + /// Do we need def2def checks? bool unorderedDefines(MachineInstr &MI); - /// \brief Resolve all operand dependencies to counter requirements + /// Resolve all operand dependencies to counter requirements Counters handleOperands(MachineInstr &MI); - /// \brief Insert S_NOP between an instruction writing M0 and S_SENDMSG. + /// Insert S_NOP between an instruction writing M0 and S_SENDMSG. void handleSendMsg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I); /// Return true if there are LGKM instrucitons that haven't been waited on @@ -435,13 +435,13 @@ bool SIInsertWaits::insertWait(MachineBasicBlock &MBB, return true; } -/// \brief helper function for handleOperands +/// helper function for handleOperands static void increaseCounters(Counters &Dst, const Counters &Src) { for (unsigned i = 0; i < 3; ++i) Dst.Array[i] = std::max(Dst.Array[i], Src.Array[i]); } -/// \brief check whether any of the counters is non-zero +/// check whether any of the counters is non-zero static bool countersNonZero(const Counters &Counter) { for (unsigned i = 0; i < 3; ++i) if (Counter.Array[i]) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 897ffa948e2..553f13ecb84 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief SI Implementation of TargetInstrInfo. +/// SI Implementation of TargetInstrInfo. // //===----------------------------------------------------------------------===// @@ -89,7 +89,7 @@ static SDValue findChainOperand(SDNode *Load) { return LastOp; } -/// \brief Returns true if both nodes have the same value for the given +/// Returns true if both nodes have the same value for the given /// operand \p Op, or if both nodes do not have this operand. static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { unsigned Opc0 = N0->getMachineOpcode(); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 61639f5cf64..673f3f89578 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Interface definition for SIInstrInfo. +/// Interface definition for SIInstrInfo. // //===----------------------------------------------------------------------===// @@ -203,7 +203,7 @@ public: bool expandPostRAPseudo(MachineInstr &MI) const override; - // \brief Returns an opcode that can be used to move a value to a \p DstRC + // Returns an opcode that can be used to move a value to a \p DstRC // register. If there is no hardware instruction that can store to \p // DstRC, then AMDGPU::COPY is returned. unsigned getMovOpcode(const TargetRegisterClass *DstRC) const; @@ -682,16 +682,16 @@ public: bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const; - /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding. + /// Return true if this 64-bit VALU instruction has a 32-bit encoding. /// This function will return false if you pass it a 32-bit instruction. bool hasVALU32BitEncoding(unsigned Opcode) const; - /// \brief Returns true if this operand uses the constant bus. + /// Returns true if this operand uses the constant bus. bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const; - /// \brief Return true if this instruction has any modifiers. + /// Return true if this instruction has any modifiers. /// e.g. src[012]_mod, omod, clamp. bool hasModifiers(unsigned Opcode) const; @@ -704,7 +704,7 @@ public: unsigned getVALUOp(const MachineInstr &MI) const; - /// \brief Return the correct register class for \p OpNo. For target-specific + /// Return the correct register class for \p OpNo. For target-specific /// instructions, this will return the register class that has been defined /// in tablegen. For generic instructions, like REG_SEQUENCE it will return /// the register class of its machine operand. @@ -712,7 +712,7 @@ public: const TargetRegisterClass *getOpRegClass(const MachineInstr &MI, unsigned OpNo) const; - /// \brief Return the size in bytes of the operand OpNo on the given + /// Return the size in bytes of the operand OpNo on the given // instruction opcode. unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const { const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo]; @@ -726,7 +726,7 @@ public: return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8; } - /// \brief This form should usually be preferred since it handles operands + /// This form should usually be preferred since it handles operands /// with unknown register classes. unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const { return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; @@ -736,7 +736,7 @@ public: /// to read a VGPR. bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const; - /// \brief Legalize the \p OpIndex operand of this instruction by inserting + /// Legalize the \p OpIndex operand of this instruction by inserting /// a MOV. For example: /// ADD_I32_e32 VGPR0, 15 /// to @@ -747,29 +747,29 @@ public: /// instead of MOV. void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const; - /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand + /// Check if \p MO is a legal operand if it was the \p OpIdx Operand /// for \p MI. bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO = nullptr) const; - /// \brief Check if \p MO would be a valid operand for the given operand + /// Check if \p MO would be a valid operand for the given operand /// definition \p OpInfo. Note this does not attempt to validate constant bus /// restrictions (e.g. literal constant usage). bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const; - /// \brief Check if \p MO (a register operand) is a legal register for the + /// Check if \p MO (a register operand) is a legal register for the /// given operand description. bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const; - /// \brief Legalize operands in \p MI by either commuting it or inserting a + /// Legalize operands in \p MI by either commuting it or inserting a /// copy of src1. void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const; - /// \brief Fix operands in \p MI to satisfy constant bus requirements. + /// Fix operands in \p MI to satisfy constant bus requirements. void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const; /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only @@ -787,11 +787,11 @@ public: MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const; - /// \brief Legalize all operands in this instruction. This function may + /// Legalize all operands in this instruction. This function may /// create new instruction and insert them before \p MI. void legalizeOperands(MachineInstr &MI) const; - /// \brief Replace this instruction's opcode with the equivalent VALU + /// Replace this instruction's opcode with the equivalent VALU /// opcode. This function will also move the users of \p MI to the /// VALU if necessary. void moveToVALU(MachineInstr &MI) const; @@ -803,11 +803,11 @@ public: MachineBasicBlock::iterator MI) const override; void insertReturn(MachineBasicBlock &MBB) const; - /// \brief Return the number of wait states that result from executing this + /// Return the number of wait states that result from executing this /// instruction. unsigned getNumWaitStates(const MachineInstr &MI) const; - /// \brief Returns the operand named \p Op. If \p MI does not have an + /// Returns the operand named \p Op. If \p MI does not have an /// operand named \c Op, this function returns nullptr. LLVM_READONLY MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const; @@ -830,7 +830,7 @@ public: bool isLowLatencyInstruction(const MachineInstr &MI) const; bool isHighLatencyInstruction(const MachineInstr &MI) const; - /// \brief Return the descriptor of the target-specific machine instruction + /// Return the descriptor of the target-specific machine instruction /// that corresponds to the specified pseudo or native opcode. const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const { return get(pseudoToMCOpcode(Opcode)); @@ -875,7 +875,7 @@ public: bool isBasicBlockPrologue(const MachineInstr &MI) const override; - /// \brief Return a partially built integer add instruction without carry. + /// Return a partially built integer add instruction without carry. /// Caller must add source operands. /// For pre-GFX9 it will generate unused carry destination operand. /// TODO: After GFX9 it should return a no-carry operation. diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index a9af8332397..96f1a1a5134 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief This pass lowers the pseudo control flow instructions to real +/// This pass lowers the pseudo control flow instructions to real /// machine instructions. /// /// All control flow is handled using predicated instructions and diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 8c38cdae5d9..8f85d077679 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -426,7 +426,7 @@ public: return ArgInfo.PrivateSegmentWaveByteOffset.getRegister(); } - /// \brief Returns the physical register reserved for use as the resource + /// Returns the physical register reserved for use as the resource /// descriptor for scratch accesses. unsigned getScratchRSrcReg() const { return ScratchRSrcReg; @@ -586,7 +586,7 @@ public: return DebuggerWorkGroupIDStackObjectIndices[Dim]; } - /// \brief Sets stack object index for \p Dim's work group ID to \p ObjectIdx. + /// Sets stack object index for \p Dim's work group ID to \p ObjectIdx. void setDebuggerWorkGroupIDStackObjectIndex(unsigned Dim, int ObjectIdx) { assert(Dim < 3); DebuggerWorkGroupIDStackObjectIndices[Dim] = ObjectIdx; @@ -598,7 +598,7 @@ public: return DebuggerWorkItemIDStackObjectIndices[Dim]; } - /// \brief Sets stack object index for \p Dim's work item ID to \p ObjectIdx. + /// Sets stack object index for \p Dim's work item ID to \p ObjectIdx. void setDebuggerWorkItemIDStackObjectIndex(unsigned Dim, int ObjectIdx) { assert(Dim < 3); DebuggerWorkItemIDStackObjectIndices[Dim] = ObjectIdx; diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index 528ce52b453..04536cdfe72 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief SI Machine Scheduler interface +/// SI Machine Scheduler interface // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.h b/llvm/lib/Target/AMDGPU/SIMachineScheduler.h index d824e38504e..0ce68ac6a89 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.h +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief SI Machine Scheduler interface +/// SI Machine Scheduler interface // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp index 6d618dfc919..574f21019bb 100644 --- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp +++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Memory legalizer - implements memory model. More information can be +/// Memory legalizer - implements memory model. More information can be /// found here: /// http://llvm.org/docs/AMDGPUUsage.html#memory-model // @@ -110,7 +110,7 @@ public: static Optional<SIMemOpInfo> getAtomicCmpxchgOrRmwInfo( const MachineBasicBlock::iterator &MI); - /// \brief Reports unknown synchronization scope used in \p MI to LLVM + /// Reports unknown synchronization scope used in \p MI to LLVM /// context. static void reportUnknownSyncScope( const MachineBasicBlock::iterator &MI); @@ -118,22 +118,22 @@ public: class SIMemoryLegalizer final : public MachineFunctionPass { private: - /// \brief Machine module info. + /// Machine module info. const AMDGPUMachineModuleInfo *MMI = nullptr; - /// \brief Instruction info. + /// Instruction info. const SIInstrInfo *TII = nullptr; - /// \brief Immediate for "vmcnt(0)". + /// Immediate for "vmcnt(0)". unsigned Vmcnt0Immediate = 0; - /// \brief Opcode for cache invalidation instruction (L1). + /// Opcode for cache invalidation instruction (L1). unsigned VmemSIMDCacheInvalidateOpc = 0; - /// \brief List of atomic pseudo instructions. + /// List of atomic pseudo instructions. std::list<MachineBasicBlock::iterator> AtomicPseudoMIs; - /// \brief Sets named bit (BitName) to "true" if present in \p MI. Returns + /// Sets named bit (BitName) to "true" if present in \p MI. Returns /// true if \p MI is modified, false otherwise. template <uint16_t BitName> bool enableNamedBit(const MachineBasicBlock::iterator &MI) const { @@ -149,44 +149,44 @@ private: return true; } - /// \brief Sets GLC bit to "true" if present in \p MI. Returns true if \p MI + /// Sets GLC bit to "true" if present in \p MI. Returns true if \p MI /// is modified, false otherwise. bool enableGLCBit(const MachineBasicBlock::iterator &MI) const { return enableNamedBit<AMDGPU::OpName::glc>(MI); } - /// \brief Sets SLC bit to "true" if present in \p MI. Returns true if \p MI + /// Sets SLC bit to "true" if present in \p MI. Returns true if \p MI /// is modified, false otherwise. bool enableSLCBit(const MachineBasicBlock::iterator &MI) const { return enableNamedBit<AMDGPU::OpName::slc>(MI); } - /// \brief Inserts "buffer_wbinvl1_vol" instruction \p Before or after \p MI. + /// Inserts "buffer_wbinvl1_vol" instruction \p Before or after \p MI. /// Always returns true. bool insertVmemSIMDCacheInvalidate(MachineBasicBlock::iterator &MI, bool Before = true) const; - /// \brief Inserts "s_waitcnt vmcnt(0)" instruction \p Before or after \p MI. + /// Inserts "s_waitcnt vmcnt(0)" instruction \p Before or after \p MI. /// Always returns true. bool insertWaitcntVmcnt0(MachineBasicBlock::iterator &MI, bool Before = true) const; - /// \brief Removes all processed atomic pseudo instructions from the current + /// Removes all processed atomic pseudo instructions from the current /// function. Returns true if current function is modified, false otherwise. bool removeAtomicPseudoMIs(); - /// \brief Expands load operation \p MI. Returns true if instructions are + /// Expands load operation \p MI. Returns true if instructions are /// added/deleted or \p MI is modified, false otherwise. bool expandLoad(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI); - /// \brief Expands store operation \p MI. Returns true if instructions are + /// Expands store operation \p MI. Returns true if instructions are /// added/deleted or \p MI is modified, false otherwise. bool expandStore(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI); - /// \brief Expands atomic fence operation \p MI. Returns true if + /// Expands atomic fence operation \p MI. Returns true if /// instructions are added/deleted or \p MI is modified, false otherwise. bool expandAtomicFence(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI); - /// \brief Expands atomic cmpxchg or rmw operation \p MI. Returns true if + /// Expands atomic cmpxchg or rmw operation \p MI. Returns true if /// instructions are added/deleted or \p MI is modified, false otherwise. bool expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI); diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp index 83074773c49..51ac8146f3a 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief This pass removes redundant S_OR_B64 instructions enabling lanes in +/// This pass removes redundant S_OR_B64 instructions enabling lanes in /// the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any /// vector instructions between them we can only keep outer SI_END_CF, given /// that CFG is structured and exec bits of the outer end statement are always diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 6a3f00f8d1e..f6e2fbc5884 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief SI implementation of the TargetRegisterInfo class. +/// SI implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// @@ -1370,7 +1370,7 @@ bool SIRegisterInfo::shouldRewriteCopySrc( return getCommonSubClass(DefRC, SrcRC) != nullptr; } -/// \brief Returns a register that is not used at any point in the function. +/// Returns a register that is not used at any point in the function. /// If all registers are used, then this function will return // AMDGPU::NoRegister. unsigned diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 81515ec8a25..1775c94c292 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Interface definition for SIRegisterInfo +/// Interface definition for SIRegisterInfo // //===----------------------------------------------------------------------===// @@ -125,7 +125,7 @@ public: return getEncodingValue(Reg) & 0xff; } - /// \brief Return the 'base' register class for this register. + /// Return the 'base' register class for this register. /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc. const TargetRegisterClass *getPhysRegClass(unsigned Reg) const; diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 61cbba4c8ae..33fd5a30791 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -126,7 +126,7 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp); } -/// \brief This function checks \p MI for operands defined by a move immediate +/// This function checks \p MI for operands defined by a move immediate /// instruction and then folds the literal constant into the instruction if it /// can. This function assumes that \p MI is a VOP1, VOP2, or VOPC instructions. static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index 53aefe82973..aeb1190e449 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief This pass adds instructions to enable whole quad mode for pixel +/// This pass adds instructions to enable whole quad mode for pixel /// shaders, and whole wavefront mode for all programs. /// /// Whole quad mode is required for derivative computations, but it interferes diff --git a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp index f61e2e413ad..e4c442db301 100644 --- a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp +++ b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp @@ -16,19 +16,19 @@ using namespace llvm; -/// \brief The target which supports all AMD GPUs. This will eventually +/// The target which supports all AMD GPUs. This will eventually /// be deprecated and there will be a R600 target and a GCN target. Target &llvm::getTheAMDGPUTarget() { static Target TheAMDGPUTarget; return TheAMDGPUTarget; } -/// \brief The target for GCN GPUs +/// The target for GCN GPUs Target &llvm::getTheGCNTarget() { static Target TheGCNTarget; return TheGCNTarget; } -/// \brief Extern function to initialize the targets for the AMDGPU backend +/// Extern function to initialize the targets for the AMDGPU backend extern "C" void LLVMInitializeAMDGPUTargetInfo() { RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600", "AMD GPUs HD2XXX-HD6XXX", "AMDGPU"); diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 8f687fdc60a..74dac6561cf 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -53,7 +53,7 @@ unsigned getBitMask(unsigned Shift, unsigned Width) { return ((1 << Width) - 1) << Shift; } -/// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width. +/// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width. /// /// \returns Packed \p Dst. unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) { @@ -62,7 +62,7 @@ unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) { return Dst; } -/// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width. +/// Unpacks bits from \p Src for given bit \p Shift and bit \p Width. /// /// \returns Unpacked bits. unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) { diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index 1fb81533cb7..5459ddfc7ef 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -45,7 +45,7 @@ enum { FIXED_NUM_SGPRS_FOR_INIT_BUG = 96 }; -/// \brief Instruction set architecture version. +/// Instruction set architecture version. struct IsaVersion { unsigned Major; unsigned Minor; @@ -55,7 +55,7 @@ struct IsaVersion { /// \returns Isa version for given subtarget \p Features. IsaVersion getIsaVersion(const FeatureBitset &Features); -/// \brief Streams isa version string for given subtarget \p STI into \p Stream. +/// Streams isa version string for given subtarget \p STI into \p Stream. void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream); /// \returns True if given subtarget \p Features support code object version 3, @@ -221,7 +221,7 @@ unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt); /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version. unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt); -/// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa +/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and /// \p Lgkmcnt respectively. /// @@ -245,7 +245,7 @@ unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt); -/// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa +/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa /// \p Version. /// /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows: @@ -292,36 +292,36 @@ bool isCI(const MCSubtargetInfo &STI); bool isVI(const MCSubtargetInfo &STI); bool isGFX9(const MCSubtargetInfo &STI); -/// \brief Is Reg - scalar register +/// Is Reg - scalar register bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI); -/// \brief Is there any intersection between registers +/// Is there any intersection between registers bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI); /// If \p Reg is a pseudo reg, return the correct hardware register given /// \p STI otherwise return \p Reg. unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI); -/// \brief Convert hardware register \p Reg to a pseudo register +/// Convert hardware register \p Reg to a pseudo register LLVM_READNONE unsigned mc2PseudoReg(unsigned Reg); -/// \brief Can this operand also contain immediate values? +/// Can this operand also contain immediate values? bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo); -/// \brief Is this floating-point operand? +/// Is this floating-point operand? bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo); -/// \brief Does this opearnd support only inlinable literals? +/// Does this opearnd support only inlinable literals? bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo); -/// \brief Get the size in bits of a register from the register class \p RC. +/// Get the size in bits of a register from the register class \p RC. unsigned getRegBitWidth(unsigned RCID); -/// \brief Get the size in bits of a register from the register class \p RC. +/// Get the size in bits of a register from the register class \p RC. unsigned getRegBitWidth(const MCRegisterClass &RC); -/// \brief Get size of register operand +/// Get size of register operand unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo); @@ -358,7 +358,7 @@ inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) { return getOperandSize(Desc.OpInfo[OpNo]); } -/// \brief Is this literal inlinable +/// Is this literal inlinable LLVM_READNONE bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi); |
