diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600InstrInfo.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600InstrInfo.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h index 9999cc516f6..0af17d01c94 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Interface definition for R600InstrInfo +/// Interface definition for R600InstrInfo // //===----------------------------------------------------------------------===// @@ -150,7 +150,7 @@ public: /// Same but using const index set instead of MI set. bool fitsConstReadLimitations(const std::vector<unsigned>&) const; - /// \brief Vector instructions are instructions that must fill all + /// Vector instructions are instructions that must fill all /// instruction slots within an instruction group. bool isVector(const MachineInstr &MI) const; @@ -209,7 +209,7 @@ public: bool expandPostRAPseudo(MachineInstr &MI) const override; - /// \brief Reserve the registers that may be accesed using indirect addressing. + /// Reserve the registers that may be accesed using indirect addressing. void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const; @@ -236,7 +236,7 @@ public: /// read or write or -1 if indirect addressing is not used by this program. int getIndirectIndexEnd(const MachineFunction &MF) const; - /// \brief Build instruction(s) for an indirect register write. + /// Build instruction(s) for an indirect register write. /// /// \returns The instruction that performs the indirect register write MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, @@ -244,7 +244,7 @@ public: unsigned ValueReg, unsigned Address, unsigned OffsetReg) const; - /// \brief Build instruction(s) for an indirect register read. + /// Build instruction(s) for an indirect register read. /// /// \returns The instruction that performs the indirect register read MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, @@ -282,23 +282,23 @@ public: MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const; - /// \brief Get the index of Op in the MachineInstr. + /// Get the index of Op in the MachineInstr. /// /// \returns -1 if the Instruction does not contain the specified \p Op. int getOperandIdx(const MachineInstr &MI, unsigned Op) const; - /// \brief Get the index of \p Op for the given Opcode. + /// Get the index of \p Op for the given Opcode. /// /// \returns -1 if the Instruction does not contain the specified \p Op. int getOperandIdx(unsigned Opcode, unsigned Op) const; - /// \brief Helper function for setting instruction flag values. + /// Helper function for setting instruction flag values. void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const; - ///\brief Add one of the MO_FLAG* flags to the specified \p Operand. + ///Add one of the MO_FLAG* flags to the specified \p Operand. void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const; - ///\brief Determine if the specified \p Flag is set on this \p Operand. + ///Determine if the specified \p Flag is set on this \p Operand. bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const; /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2) @@ -308,7 +308,7 @@ public: MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0, unsigned Flag = 0) const; - /// \brief Clear the specified flag on the instruction. + /// Clear the specified flag on the instruction. void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const; // Helper functions that check the opcode for status information |
