diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 7db266f72d5..a75ce7200d4 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -779,10 +779,10 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { case 105: return createRegOperand(XNACK_MASK_HI); case 106: return createRegOperand(VCC_LO); case 107: return createRegOperand(VCC_HI); - case 108: assert(!isGFX9()); return createRegOperand(TBA_LO); - case 109: assert(!isGFX9()); return createRegOperand(TBA_HI); - case 110: assert(!isGFX9()); return createRegOperand(TMA_LO); - case 111: assert(!isGFX9()); return createRegOperand(TMA_HI); + case 108: return createRegOperand(TBA_LO); + case 109: return createRegOperand(TBA_HI); + case 110: return createRegOperand(TMA_LO); + case 111: return createRegOperand(TMA_HI); case 124: return createRegOperand(M0); case 126: return createRegOperand(EXEC_LO); case 127: return createRegOperand(EXEC_HI); @@ -790,7 +790,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { case 236: return createRegOperand(SRC_SHARED_LIMIT); case 237: return createRegOperand(SRC_PRIVATE_BASE); case 238: return createRegOperand(SRC_PRIVATE_LIMIT); - // TODO: SRC_POPS_EXITING_WAVE_ID + case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); // ToDo: no support for vccz register case 251: break; // ToDo: no support for execz register @@ -809,9 +809,14 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { case 102: return createRegOperand(FLAT_SCR); case 104: return createRegOperand(XNACK_MASK); case 106: return createRegOperand(VCC); - case 108: assert(!isGFX9()); return createRegOperand(TBA); - case 110: assert(!isGFX9()); return createRegOperand(TMA); + case 108: return createRegOperand(TBA); + case 110: return createRegOperand(TMA); case 126: return createRegOperand(EXEC); + case 235: return createRegOperand(SRC_SHARED_BASE); + case 236: return createRegOperand(SRC_SHARED_LIMIT); + case 237: return createRegOperand(SRC_PRIVATE_BASE); + case 238: return createRegOperand(SRC_PRIVATE_LIMIT); + case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); default: break; } return errOperand(Val, "unknown operand encoding " + Twine(Val)); |
