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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-03-20 15:40:52 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2019-03-20 15:40:52 +0000 |
| commit | 137976fae22df17daa16dd9002a2c74cd38b9c67 (patch) | |
| tree | 762176ef05d5573bf5d595d7a731fee5beaaa316 /llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | |
| parent | 9e7af8d02688254ecf762cc82cd28d178afac57f (diff) | |
| download | bcm5719-llvm-137976fae22df17daa16dd9002a2c74cd38b9c67.tar.gz bcm5719-llvm-137976fae22df17daa16dd9002a2c74cd38b9c67.zip | |
[AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, private_base, private_limit, pops_exiting_wave_id
See bug 39297: https://bugs.llvm.org/show_bug.cgi?id=39297
Reviewers: artem.tamazov, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D59290
llvm-svn: 356561
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 7db266f72d5..a75ce7200d4 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -779,10 +779,10 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { case 105: return createRegOperand(XNACK_MASK_HI); case 106: return createRegOperand(VCC_LO); case 107: return createRegOperand(VCC_HI); - case 108: assert(!isGFX9()); return createRegOperand(TBA_LO); - case 109: assert(!isGFX9()); return createRegOperand(TBA_HI); - case 110: assert(!isGFX9()); return createRegOperand(TMA_LO); - case 111: assert(!isGFX9()); return createRegOperand(TMA_HI); + case 108: return createRegOperand(TBA_LO); + case 109: return createRegOperand(TBA_HI); + case 110: return createRegOperand(TMA_LO); + case 111: return createRegOperand(TMA_HI); case 124: return createRegOperand(M0); case 126: return createRegOperand(EXEC_LO); case 127: return createRegOperand(EXEC_HI); @@ -790,7 +790,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { case 236: return createRegOperand(SRC_SHARED_LIMIT); case 237: return createRegOperand(SRC_PRIVATE_BASE); case 238: return createRegOperand(SRC_PRIVATE_LIMIT); - // TODO: SRC_POPS_EXITING_WAVE_ID + case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); // ToDo: no support for vccz register case 251: break; // ToDo: no support for execz register @@ -809,9 +809,14 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { case 102: return createRegOperand(FLAT_SCR); case 104: return createRegOperand(XNACK_MASK); case 106: return createRegOperand(VCC); - case 108: assert(!isGFX9()); return createRegOperand(TBA); - case 110: assert(!isGFX9()); return createRegOperand(TMA); + case 108: return createRegOperand(TBA); + case 110: return createRegOperand(TMA); case 126: return createRegOperand(EXEC); + case 235: return createRegOperand(SRC_SHARED_BASE); + case 236: return createRegOperand(SRC_SHARED_LIMIT); + case 237: return createRegOperand(SRC_PRIVATE_BASE); + case 238: return createRegOperand(SRC_PRIVATE_LIMIT); + case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); default: break; } return errOperand(Val, "unknown operand encoding " + Twine(Val)); |
