diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/DSInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/DSInstructions.td | 82 |
1 files changed, 47 insertions, 35 deletions
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index 468d67f3b68..8dad3e83e04 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -203,20 +203,28 @@ class DS_1A <string opName> : DS_Pseudo<opName, let has_data1 = 0; } -class DS_1A_GDS <string opName> : DS_Pseudo<opName, - (outs), - (ins VGPR_32:$addr), - "$addr gds"> { +class DS_GWS <string opName, dag ins, string asmOps> +: DS_Pseudo<opName, (outs), ins, asmOps> { - let has_vdst = 0; - let has_data0 = 0; - let has_data1 = 0; - let has_offset = 0; - let has_offset0 = 0; - let has_offset1 = 0; + let has_vdst = 0; + let has_addr = 0; + let has_data0 = 0; + let has_data1 = 0; + + let has_gds = 0; + let gdsValue = 1; + let AsmMatchConverter = "cvtDSGds"; +} + +class DS_GWS_0D <string opName> +: DS_GWS<opName, + (ins offset:$offset, gds:$gds), "$offset gds">; + +class DS_GWS_1D <string opName> +: DS_GWS<opName, + (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> { - let has_gds = 0; - let gdsValue = 1; + let has_data0 = 1; } class DS_VOID <string opName> : DS_Pseudo<opName, @@ -390,11 +398,11 @@ def DS_WRXCHG2_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64 def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>, AtomicNoRet<"ds_wrxchg2st64_b64", 1>; -def DS_GWS_INIT : DS_1A_GDS<"ds_gws_init">; -def DS_GWS_SEMA_V : DS_1A_GDS<"ds_gws_sema_v">; -def DS_GWS_SEMA_BR : DS_1A_GDS<"ds_gws_sema_br">; -def DS_GWS_SEMA_P : DS_1A_GDS<"ds_gws_sema_p">; -def DS_GWS_BARRIER : DS_1A_GDS<"ds_gws_barrier">; +def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">; +def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">; +def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">; +def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">; +def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">; def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">; def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">; @@ -405,7 +413,7 @@ def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">; def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">; def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">; def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">; -def DS_AND_SRC2_B32 : DS_1A<"ds_and_src_b32">; +def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">; def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">; def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">; def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">; @@ -448,25 +456,22 @@ def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>; def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>; } -let SubtargetPredicate = isSICI in { def DS_CONSUME : DS_0A_RET<"ds_consume">; def DS_APPEND : DS_0A_RET<"ds_append">; def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">; -} //===----------------------------------------------------------------------===// // Instruction definitions for CI and newer. //===----------------------------------------------------------------------===// -// Remaining instructions: -// DS_GWS_SEMA_RELEASE_ALL -// DS_WRAP_RTN_B32 -// DS_CNDXCHG32_RTN_B64 -// DS_CONDXCHG32_RTN_B128 let SubtargetPredicate = isCIVI in { -def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">, - AtomicNoRet<"ds_wrap_f32", 1>; +def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>; + +def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>, + AtomicNoRet<"", 1>; + +def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">; let mayStore = 0 in { def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>; @@ -678,8 +683,10 @@ def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>; def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>; def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>; -// FIXME: this instruction is actually CI/VI -def DS_WRAP_RTN_F32_si : DS_Real_si<0x34, DS_WRAP_RTN_F32>; +// These instruction are CI/VI only +def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>; +def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>; +def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>; def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>; def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>; @@ -820,11 +827,11 @@ def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>; def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>; def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>; def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>; -def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>; -def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>; -def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>; -def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>; -def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>; +def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>; +def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>; +def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>; +def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>; +def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>; def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>; def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>; def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>; @@ -847,7 +854,7 @@ def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>; def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>; def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>; def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>; -def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>; +def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>; def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>; def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>; def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>; @@ -856,6 +863,9 @@ def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>; def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>; def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>; def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>; +def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>; +def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>; +def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>; def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>; def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>; def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>; @@ -897,6 +907,8 @@ def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>; def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>; def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>; def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>; +def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>; +def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>; def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>; def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>; def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>; |
