diff options
Diffstat (limited to 'llvm/lib/Target/AArch64')
4 files changed, 15 insertions, 12 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 66f37c88ae5..05775a84bef 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1179,7 +1179,8 @@ static void changeVectorFPCCToAArch64CC(ISD::CondCode CC, changeFPCCToAArch64CC(CC, CondCode, CondCode2); break; case ISD::SETUO: - Invert = true; // Fallthrough + Invert = true; + LLVM_FALLTHROUGH; case ISD::SETO: CondCode = AArch64CC::MI; CondCode2 = AArch64CC::GE; @@ -6720,8 +6721,8 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS, case AArch64CC::LT: if (!NoNans) return SDValue(); - // If we ignore NaNs then we can use to the MI implementation. - // Fallthrough. + // If we ignore NaNs then we can use to the MI implementation. + LLVM_FALLTHROUGH; case AArch64CC::MI: if (IsZero) return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 45b90a53387..e3afa8924e1 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -375,7 +375,8 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, // if NZCV is used, do not fold. if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) return 0; - // fall-through to ADDXri and ADDWri. + // fall-through to ADDXri and ADDWri. + LLVM_FALLTHROUGH; case AArch64::ADDXri: case AArch64::ADDWri: // add x, 1 -> csinc. @@ -402,7 +403,8 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, // if NZCV is used, do not fold. if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) return 0; - // fall-through to SUBXrr and SUBWrr. + // fall-through to SUBXrr and SUBWrr. + LLVM_FALLTHROUGH; case AArch64::SUBXrr: case AArch64::SUBWrr: { // neg x -> csneg, represented as sub dst, xzr, src. diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 25c2c958358..092e94c53ed 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3455,7 +3455,7 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, if (RI->isSubRegisterEq(Rn, Rt2)) return Error(Loc[1], "unpredictable LDP instruction, writeback base " "is also a destination"); - // FALLTHROUGH + LLVM_FALLTHROUGH; } case AArch64::LDPDi: case AArch64::LDPQi: diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index fe6ea31b906..b97fe1721ea 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -1097,7 +1097,7 @@ static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, case AArch64::STXRB: case AArch64::STXRH: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); - // FALLTHROUGH + LLVM_FALLTHROUGH; case AArch64::LDARW: case AArch64::LDARB: case AArch64::LDARH: @@ -1121,7 +1121,7 @@ static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, case AArch64::STLXRX: case AArch64::STXRX: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); - // FALLTHROUGH + LLVM_FALLTHROUGH; case AArch64::LDARX: case AArch64::LDAXRX: case AArch64::LDXRX: @@ -1133,7 +1133,7 @@ static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, case AArch64::STLXPW: case AArch64::STXPW: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); - // FALLTHROUGH + LLVM_FALLTHROUGH; case AArch64::LDAXPW: case AArch64::LDXPW: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); @@ -1142,7 +1142,7 @@ static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, case AArch64::STLXPX: case AArch64::STXPX: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); - // FALLTHROUGH + LLVM_FALLTHROUGH; case AArch64::LDAXPX: case AArch64::LDXPX: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); @@ -1218,7 +1218,7 @@ static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, case AArch64::STPXpre: case AArch64::LDPSWpre: NeedsDisjointWritebackTransfer = true; - // Fallthrough + LLVM_FALLTHROUGH; case AArch64::LDNPXi: case AArch64::STNPXi: case AArch64::LDPXi: @@ -1232,7 +1232,7 @@ static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, case AArch64::LDPWpre: case AArch64::STPWpre: NeedsDisjointWritebackTransfer = true; - // Fallthrough + LLVM_FALLTHROUGH; case AArch64::LDNPWi: case AArch64::STNPWi: case AArch64::LDPWi: |
