diff options
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 30 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 123 |
2 files changed, 127 insertions, 26 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 686bd0a28f6..e2ed98bd423 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -690,11 +690,31 @@ let Predicates = [HasSVE] in { defm INDEX_RI : sve_int_index_ri<"index">; defm INDEX_II : sve_int_index_ii<"index">; - defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">; - defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">; - - defm LSR_ZPmZ : sve_int_bin_pred_shift_1<0b001, "lsr">; - defm LSL_ZPmZ : sve_int_bin_pred_shift_1<0b011, "lsl">; + // Unpredicated shifts + defm ASR_ZZI : sve_int_bin_cons_shift_imm_right<0b00, "asr">; + defm LSR_ZZI : sve_int_bin_cons_shift_imm_right<0b01, "lsr">; + defm LSL_ZZI : sve_int_bin_cons_shift_imm_left< 0b11, "lsl">; + + defm ASR_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b00, "asr">; + defm LSR_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b01, "lsr">; + defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">; + + // Predicated shifts + defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b000, "asr">; + defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b001, "lsr">; + defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b011, "lsl">; + defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b100, "asrd">; + + defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">; + defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">; + defm LSL_ZPmZ : sve_int_bin_pred_shift<0b011, "lsl">; + defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr">; + defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr">; + defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr">; + + defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr">; + defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr">; + defm LSL_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b011, "lsl">; def FCVT_ZPmZ_StoH : sve_fp_2op_p_zd<0b1001000, "fcvt", ZPR32, ZPR16>; def FCVT_ZPmZ_HtoS : sve_fp_2op_p_zd<0b1001001, "fcvt", ZPR16, ZPR32>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 6fd617f3087..cc6b5489689 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1688,9 +1688,59 @@ multiclass sve_int_index_rr<string asm> { // SVE Bitwise Shift - Predicated Group //===----------------------------------------------------------------------===// -class sve_int_bin_pred_shift_1<bits<2> sz8_64, bits<3> opc, string asm, - ZPRRegOp zprty> -: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), +class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm, + ZPRRegOp zprty, Operand immtype> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), + asm, "\t$Zdn, $Pg/m, $_Zdn, $imm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zdn; + bits<6> imm; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = tsz8_64{3-2}; + let Inst{21-19} = 0b000; + let Inst{18-16} = opc; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-8} = tsz8_64{1-0}; + let Inst{7-5} = imm{2-0}; // imm3 + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> { + def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; + def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { + let Inst{8} = imm{3}; + } + def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { + let Inst{9-8} = imm{4-3}; + } + def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { + let Inst{22} = imm{5}; + let Inst{9-8} = imm{4-3}; + } +} + +multiclass sve_int_bin_pred_shift_imm_right<bits<3> opc, string asm> { + def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; + def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { + let Inst{8} = imm{3}; + } + def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { + let Inst{9-8} = imm{4-3}; + } + def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { + let Inst{22} = imm{5}; + let Inst{9-8} = imm{4-3}; + } +} + +class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc, + string asm, ZPRRegOp zprty, ZPRRegOp zprty2> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm), asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { @@ -1699,7 +1749,8 @@ class sve_int_bin_pred_shift_1<bits<2> sz8_64, bits<3> opc, string asm, bits<5> Zm; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; - let Inst{21-19} = 0b010; + let Inst{21-20} = 0b01; + let Inst{19} = wide; let Inst{18-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; @@ -1709,19 +1760,49 @@ class sve_int_bin_pred_shift_1<bits<2> sz8_64, bits<3> opc, string asm, let Constraints = "$Zdn = $_Zdn"; } -multiclass sve_int_bin_pred_shift_1<bits<3> opc, string asm> { - def _B : sve_int_bin_pred_shift_1<0b00, opc, asm, ZPR8>; - def _H : sve_int_bin_pred_shift_1<0b01, opc, asm, ZPR16>; - def _S : sve_int_bin_pred_shift_1<0b10, opc, asm, ZPR32>; - def _D : sve_int_bin_pred_shift_1<0b11, opc, asm, ZPR64>; +multiclass sve_int_bin_pred_shift<bits<3> opc, string asm> { + def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>; + def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>; + def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>; + def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>; } +multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm> { + def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>; + def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>; + def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>; +} //===----------------------------------------------------------------------===// -// SVE Shift by Immediate - Unpredicated Group +// SVE Shift - Unpredicated Group //===----------------------------------------------------------------------===// -class sve_int_bin_cons_shift_b<bits<4> tsz8_64, bits<2> opc, string asm, +class sve_int_bin_cons_shift_wide<bits<2> sz8_64, bits<2> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-12} = 0b1000; + let Inst{11-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_bin_cons_shift_wide<bits<2> opc, string asm> { + def _B : sve_int_bin_cons_shift_wide<0b00, opc, asm, ZPR8>; + def _H : sve_int_bin_cons_shift_wide<0b01, opc, asm, ZPR16>; + def _S : sve_int_bin_cons_shift_wide<0b10, opc, asm, ZPR32>; +} + +class sve_int_bin_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm, ZPRRegOp zprty, Operand immtype> : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm), asm, "\t$Zd, $Zn, $imm", @@ -1740,29 +1821,29 @@ class sve_int_bin_cons_shift_b<bits<4> tsz8_64, bits<2> opc, string asm, let Inst{4-0} = Zd; } -multiclass sve_int_bin_cons_shift_b_left<bits<2> opc, string asm> { - def _B : sve_int_bin_cons_shift_b<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; - def _H : sve_int_bin_cons_shift_b<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { +multiclass sve_int_bin_cons_shift_imm_left<bits<2> opc, string asm> { + def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; + def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { let Inst{19} = imm{3}; } - def _S : sve_int_bin_cons_shift_b<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { + def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { let Inst{20-19} = imm{4-3}; } - def _D : sve_int_bin_cons_shift_b<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { + def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { let Inst{22} = imm{5}; let Inst{20-19} = imm{4-3}; } } -multiclass sve_int_bin_cons_shift_b_right<bits<2> opc, string asm> { - def _B : sve_int_bin_cons_shift_b<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; - def _H : sve_int_bin_cons_shift_b<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { +multiclass sve_int_bin_cons_shift_imm_right<bits<2> opc, string asm> { + def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; + def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { let Inst{19} = imm{3}; } - def _S : sve_int_bin_cons_shift_b<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { + def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { let Inst{20-19} = imm{4-3}; } - def _D : sve_int_bin_cons_shift_b<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { + def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { let Inst{22} = imm{5}; let Inst{20-19} = imm{4-3}; } |
