diff options
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 32 |
4 files changed, 53 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 42328a38acc..5e286c63cc7 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -262,6 +262,12 @@ def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { let DecoderMethod = "DecodeSImm<9>"; } +def SImm8Operand : SImmOperand<8>; +def simm8 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -128 && Imm < 127; }]> { + let ParserMatchClass = SImm8Operand; + let DecoderMethod = "DecodeSImm<8>"; +} + def SImm6Operand : SImmOperand<6>; def simm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -32 && Imm < 32; }]> { let ParserMatchClass = SImm6Operand; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index ae818716af4..9f16d74b37a 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -52,6 +52,11 @@ let Predicates = [HasSVE] in { defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">; defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">; + defm SMAX_ZI : sve_int_arith_imm1<0b00, "smax", simm8>; + defm SMIN_ZI : sve_int_arith_imm1<0b10, "smin", simm8>; + defm UMAX_ZI : sve_int_arith_imm1<0b01, "umax", imm0_255>; + defm UMIN_ZI : sve_int_arith_imm1<0b11, "umin", imm0_255>; + defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb">; defm UXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b001, "uxtb">; defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth">; @@ -61,6 +66,13 @@ let Predicates = [HasSVE] in { defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs">; defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg">; + defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax">; + defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax">; + defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">; + defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin">; + defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">; + defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd">; + defm FADD_ZPmI : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>; defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>; defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index a7a74d37454..f5e762e87ce 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3915,6 +3915,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, return Error(Loc, "index must be a multiple of 16 in range [-128, 112]."); case Match_InvalidMemoryIndexed1SImm6: return Error(Loc, "index must be an integer in range [-32, 31]."); + case Match_InvalidMemoryIndexedSImm8: + return Error(Loc, "index must be an integer in range [-128, 127]."); case Match_InvalidMemoryIndexedSImm9: return Error(Loc, "index must be an integer in range [-256, 255]."); case Match_InvalidMemoryIndexed8SImm10: @@ -4563,6 +4565,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidMemoryIndexed8UImm6: case Match_InvalidMemoryIndexedSImm6: case Match_InvalidMemoryIndexedSImm5: + case Match_InvalidMemoryIndexedSImm8: case Match_InvalidMemoryIndexedSImm9: case Match_InvalidMemoryIndexed8SImm10: case Match_InvalidImm0_1: diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 81687a0ba10..4b3bd094836 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1057,6 +1057,13 @@ multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> { def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>; } +multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> { + def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>; + def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>; + def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>; + def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>; +} + //===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Unary Predicated Group //===----------------------------------------------------------------------===// @@ -1207,6 +1214,31 @@ multiclass sve_int_arith_imm0<bits<3> opc, string asm> { def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>; } +class sve_int_arith_imm1<bits<2> sz8_64, bits<2> opc, string asm, + ZPRRegOp zprty, Operand immtype> +: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm), + asm, "\t$Zdn, $_Zdn, $imm", + "", + []>, Sched<[]> { + bits<5> Zdn; + bits<8> imm; + let Inst{31-24} = 0b00100101; + let Inst{23-22} = sz8_64; + let Inst{21-18} = 0b1010; + let Inst{17-16} = opc; + let Inst{15-13} = 0b110; + let Inst{12-5} = imm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_int_arith_imm1<bits<2> opc, string asm, Operand immtype> { + def _B : sve_int_arith_imm1<0b00, opc, asm, ZPR8, immtype>; + def _H : sve_int_arith_imm1<0b01, opc, asm, ZPR16, immtype>; + def _S : sve_int_arith_imm1<0b10, opc, asm, ZPR32, immtype>; + def _D : sve_int_arith_imm1<0b11, opc, asm, ZPR64, immtype>; +} //===----------------------------------------------------------------------===// // SVE Bitwise Logical - Unpredicated Group |
