summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64CallLowering.cpp')
-rw-r--r--llvm/lib/Target/AArch64/AArch64CallLowering.cpp25
1 files changed, 8 insertions, 17 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
index 4f2add28ff8..6fa29754f70 100644
--- a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
@@ -131,19 +131,14 @@ bool AArch64CallLowering::lowerFormalArguments(
}
bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
- const CallInst &CI, unsigned CalleeReg,
- unsigned ResReg,
+ MachineOperand &Callee,
+ ArrayRef<MVT> ResTys,
+ ArrayRef<unsigned> ResRegs,
+ ArrayRef<MVT> ArgTys,
ArrayRef<unsigned> ArgRegs) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = *MF.getFunction();
- // First step is to marshall all the function's parameters into the correct
- // physregs and memory locations. Gather the sequence of argument types that
- // we'll pass to the assigner function.
- SmallVector<MVT, 8> ArgTys;
- for (auto &Arg : CI.arg_operands())
- ArgTys.push_back(MVT::getVT(Arg->getType()));
-
// Find out which ABI gets to decide where things go.
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
CCAssignFn *CallAssignFn =
@@ -160,12 +155,8 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
});
// Now we can build the actual call instruction.
- MachineInstrBuilder MIB;
- if (CalleeReg)
- MIB = MIRBuilder.buildInstr(AArch64::BLR).addUse(CalleeReg);
- else
- MIB = MIRBuilder.buildInstr(AArch64::BL)
- .addGlobalAddress(CI.getCalledFunction());
+ auto MIB = MIRBuilder.buildInstr(Callee.isReg() ? AArch64::BLR : AArch64::BL);
+ MIB.addOperand(Callee);
// Tell the call which registers are clobbered.
auto TRI = MF.getSubtarget().getRegisterInfo();
@@ -178,9 +169,9 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// symmetry with the arugments, the physical register must be an
// implicit-define of the call instruction.
CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
- if (!CI.getType()->isVoidTy())
+ if (!ResRegs.empty())
handleAssignments(
- MIRBuilder, RetAssignFn, MVT::getVT(CI.getType()), ResReg,
+ MIRBuilder, RetAssignFn, ResTys, ResRegs,
[&](MachineIRBuilder &MIRBuilder, unsigned ValReg, unsigned PhysReg) {
MIRBuilder.buildCopy(ValReg, PhysReg);
MIB.addDef(PhysReg, RegState::Implicit);
OpenPOWER on IntegriCloud