diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 3 |
4 files changed, 3 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 5a8f5190df2..6650a1e2073 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -385,7 +385,7 @@ bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) { bool IRTranslator::translatePHI(const User &U) { const PHINode &PI = cast<PHINode>(U); - auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI); + auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI); MIB.addDef(getOrCreateVReg(PI)); PendingPHIs.emplace_back(&PI, MIB.getInstr()); diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp index 786deccbd05..9844dbb0120 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp @@ -33,11 +33,6 @@ MachineLegalizer::MachineLegalizer() : TablesInitialized(false) { DefaultActions[TargetOpcode::G_ANYEXT] = Legal; DefaultActions[TargetOpcode::G_TRUNC] = Legal; - // G_TYPE and G_PHI are essentially an annotated COPY/PHI instructions so - // they're always legal. - DefaultActions[TargetOpcode::G_TYPE] = Legal; - DefaultActions[TargetOpcode::G_PHI] = Legal; - DefaultActions[TargetOpcode::G_INTRINSIC] = Legal; DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal; diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 71985268406..1f342ee5622 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -224,8 +224,7 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const { bool CompleteMapping = true; // For copies we want to walk over the operands and try to find one // that has a register bank. - bool isCopyLike = - MI.isCopy() || MI.isPHI() || MI.getOpcode() == TargetOpcode::G_TYPE; + bool isCopyLike = MI.isCopy() || MI.isPHI(); // Remember the register bank for reuse for copy-like instructions. const RegisterBank *RegBank = nullptr; // Remember the size of the register for reuse for copy-like instructions. diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index f06394279c9..808f81a567b 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -908,8 +908,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { } // Generic opcodes must not have physical register operands. - if (isPreISelGenericOpcode(MCID.getOpcode()) && - MCID.getOpcode() != TargetOpcode::G_TYPE) { + if (isPreISelGenericOpcode(MCID.getOpcode())) { for (auto &Op : MI->operands()) { if (Op.isReg() && TargetRegisterInfo::isPhysicalRegister(Op.getReg())) report("Generic instruction cannot have physical register", MI); |
