diff options
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 3718e64d9ce..d0e9afc3a3f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -16,6 +16,7 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "sched" +#include "llvm/CodeGen/MachinePassRegistry.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/MRegisterInfo.h" @@ -31,6 +32,15 @@ #include "llvm/Support/CommandLine.h" using namespace llvm; +static RegisterScheduler + burrListDAGScheduler("list-burr", + " Bottom-up register reduction list scheduling", + createBURRListDAGScheduler); +static RegisterScheduler + tdrListrDAGScheduler("list-tdrr", + " Top-down register reduction list scheduling", + createTDRRListDAGScheduler); + namespace { //===----------------------------------------------------------------------===// /// ScheduleDAGRRList - The actual register reduction list scheduler @@ -876,15 +886,15 @@ void TDRegReductionPriorityQueue<SF>::CalculatePriorities() { // Public Constructor Functions //===----------------------------------------------------------------------===// -llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG, +llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG *DAG, MachineBasicBlock *BB) { - return new ScheduleDAGRRList(DAG, BB, DAG.getTarget(), true, + return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, new BURegReductionPriorityQueue<bu_ls_rr_sort>()); } -llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG &DAG, +llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG *DAG, MachineBasicBlock *BB) { - return new ScheduleDAGRRList(DAG, BB, DAG.getTarget(), false, + return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, new TDRegReductionPriorityQueue<td_ls_rr_sort>()); } |
