summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/MachineRegisterInfo.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/CodeGen/MachineRegisterInfo.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineRegisterInfo.cpp17
1 files changed, 10 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 6693ccacb77..5b42cd01efc 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -93,6 +93,13 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
return true;
}
+unsigned MachineRegisterInfo::createIncompleteVirtualRegister() {
+ unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
+ VRegInfo.grow(Reg);
+ RegAllocHints.grow(Reg);
+ return Reg;
+}
+
/// createVirtualRegister - Create and return a new virtual register in the
/// function with the specified register class.
///
@@ -103,10 +110,8 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
"Virtual register RegClass must be allocatable.");
// New virtual register number.
- unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
- VRegInfo.grow(Reg);
+ unsigned Reg = createIncompleteVirtualRegister();
VRegInfo[Reg].first = RegClass;
- RegAllocHints.grow(Reg);
if (TheDelegate)
TheDelegate->MRI_NoteNewVirtualRegister(Reg);
return Reg;
@@ -127,12 +132,10 @@ void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
unsigned
MachineRegisterInfo::createGenericVirtualRegister(LLT Ty) {
// New virtual register number.
- unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
- VRegInfo.grow(Reg);
- // FIXME: Should we use a dummy register bank?
+ unsigned Reg = createIncompleteVirtualRegister();
+ // FIXME: Should we use a dummy register class?
VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
getVRegToType()[Reg] = Ty;
- RegAllocHints.grow(Reg);
if (TheDelegate)
TheDelegate->MRI_NoteNewVirtualRegister(Reg);
return Reg;
OpenPOWER on IntegriCloud