summaryrefslogtreecommitdiffstats
path: root/clang/test/CodeGen/attr-target.c
diff options
context:
space:
mode:
Diffstat (limited to 'clang/test/CodeGen/attr-target.c')
-rw-r--r--clang/test/CodeGen/attr-target.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/clang/test/CodeGen/attr-target.c b/clang/test/CodeGen/attr-target.c
index d805d133f36..b02dd719650 100644
--- a/clang/test/CodeGen/attr-target.c
+++ b/clang/test/CodeGen/attr-target.c
@@ -14,6 +14,7 @@ int __attribute__((target("sse4"))) panda(int a) { return 4; }
int bar(int a) { return baz(a) + foo(a); }
int __attribute__((target("avx, sse4.2, arch= ivybridge"))) qux(int a) { return 4; }
+int __attribute__((target("mno-aes, arch=ivybridge"))) qax(int a) { return 4; }
// Check that we emit the additional subtarget and cpu features for foo and not for baz or bar.
// CHECK: baz{{.*}} #0
@@ -25,7 +26,9 @@ int __attribute__((target("avx, sse4.2, arch= ivybridge"))) qux(int
// CHECK: echidna{{.*}} #2
// CHECK: bar{{.*}} #0
// CHECK: qux{{.*}} #1
+// CHECK: qax{{.*}} #4
// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+pclmul,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop"
// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
+// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+pclmul,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,-aes"
OpenPOWER on IntegriCloud