diff options
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index c562cf7a717..aa59c98296c 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1048,7 +1048,7 @@ static const uint16_t QPRDecoderTable[] = { static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo > 31) + if (RegNo > 31 || (RegNo & 1) != 0) return MCDisassembler::Fail; RegNo >>= 1; diff --git a/llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt index f961c64f7d9..e8e5d6fa21c 100644 --- a/llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ b/llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -1,5 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" -# XFAIL: * +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -9,3 +8,4 @@ # # Qm -> bit[0] == 0, otherwise UNDEFINED 0xdb 0xe0 0x40 0xf2 +# CHECK: invalid instruction encoding |
