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| author | Mihai Popa <mihail.popa@gmail.com> | 2013-05-20 14:42:43 +0000 |
|---|---|---|
| committer | Mihai Popa <mihail.popa@gmail.com> | 2013-05-20 14:42:43 +0000 |
| commit | dcf092272072ebfdbbde31326d33003bb33776d4 (patch) | |
| tree | 6c03f08807f08d54c9467c4d10288235206f3573 | |
| parent | 92bbd3e818388503156fa632786d2205bba67069 (diff) | |
| download | bcm5719-llvm-dcf092272072ebfdbbde31326d33003bb33776d4.tar.gz bcm5719-llvm-dcf092272072ebfdbbde31326d33003bb33776d4.zip | |
Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).
llvm-svn: 182279
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index c562cf7a717..aa59c98296c 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1048,7 +1048,7 @@ static const uint16_t QPRDecoderTable[] = { static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo > 31) + if (RegNo > 31 || (RegNo & 1) != 0) return MCDisassembler::Fail; RegNo >>= 1; diff --git a/llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt index f961c64f7d9..e8e5d6fa21c 100644 --- a/llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ b/llvm/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -1,5 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" -# XFAIL: * +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 @@ -9,3 +8,4 @@ # # Qm -> bit[0] == 0, otherwise UNDEFINED 0xdb 0xe0 0x40 0xf2 +# CHECK: invalid instruction encoding |
