diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 45 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.h | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll | 27 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 12 |
4 files changed, 33 insertions, 52 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 3ba04831d15..13b92fc07a1 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -679,7 +679,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, setTargetDAGCombine(ISD::SCALAR_TO_VECTOR); setTargetDAGCombine(ISD::ZERO_EXTEND); setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); - setTargetDAGCombine(ISD::BUILD_VECTOR); // All memory operations. Some folding on the pointer operand is done to help // matching the constant offsets in the addressing modes. @@ -8133,48 +8132,6 @@ SDValue SITargetLowering::performExtractVectorEltCombine( return SDValue(); } -static bool convertBuildVectorCastElt(SelectionDAG &DAG, - SDValue &Lo, SDValue &Hi) { - if (Hi.getOpcode() == ISD::BITCAST && - Hi.getOperand(0).getValueType() == MVT::f16 && - (isa<ConstantSDNode>(Lo) || Lo.isUndef())) { - Lo = DAG.getNode(ISD::BITCAST, SDLoc(Lo), MVT::f16, Lo); - Hi = Hi.getOperand(0); - return true; - } - - return false; -} - -SDValue SITargetLowering::performBuildVectorCombine( - SDNode *N, DAGCombinerInfo &DCI) const { - SDLoc SL(N); - - if (!isTypeLegal(MVT::v2i16)) - return SDValue(); - SelectionDAG &DAG = DCI.DAG; - EVT VT = N->getValueType(0); - - if (VT == MVT::v2i16) { - SDValue Lo = N->getOperand(0); - SDValue Hi = N->getOperand(1); - - // v2i16 build_vector (const|undef), (bitcast f16:$x) - // -> bitcast (v2f16 build_vector const|undef, $x - if (convertBuildVectorCastElt(DAG, Lo, Hi)) { - SDValue NewVec = DAG.getBuildVector(MVT::v2f16, SL, { Lo, Hi }); - return DAG.getNode(ISD::BITCAST, SL, VT, NewVec); - } - - if (convertBuildVectorCastElt(DAG, Hi, Lo)) { - SDValue NewVec = DAG.getBuildVector(MVT::v2f16, SL, { Hi, Lo }); - return DAG.getNode(ISD::BITCAST, SL, VT, NewVec); - } - } - - return SDValue(); -} - unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG, const SDNode *N0, const SDNode *N1) const { @@ -8783,8 +8740,6 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, } case ISD::EXTRACT_VECTOR_ELT: return performExtractVectorEltCombine(N, DCI); - case ISD::BUILD_VECTOR: - return performBuildVectorCombine(N, DCI); } return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index bcb46ec41d1..09e0a12cce8 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -154,7 +154,6 @@ private: SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; - SDValue performBuildVectorCombine(SDNode *N, DAGCombinerInfo &DCI) const; unsigned getFusedOpcode(const SelectionDAG &DAG, const SDNode *N0, const SDNode *N1) const; diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll b/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll new file mode 100644 index 00000000000..865dccb2791 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; There was an infinite loop in DAGCombiner from a target build_vector +; combine and a generic insert_vector_elt combine. + +; GCN-LABEL: {{^}}combine_loop: +; GCN: flat_load_ushort +; GCN: flat_store_short +; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, +define amdgpu_kernel void @combine_loop(i16* %arg) #0 { +bb: + br label %bb1 + +bb1: + %tmp = phi <2 x i16> [ <i16 15360, i16 15360>, %bb ], [ %tmp5, %bb1 ] + %tmp2 = phi half [ 0xH0000, %bb ], [ %tmp8, %bb1 ] + %tmp3 = load volatile half, half* null, align 536870912 + %tmp4 = bitcast half %tmp3 to i16 + %tmp5 = insertelement <2 x i16> <i16 0, i16 undef>, i16 %tmp4, i32 1 + %tmp6 = bitcast i16* %arg to half* + store half %tmp2, half* %tmp6, align 2 + %tmp7 = bitcast <2 x i16> %tmp to <2 x half> + %tmp8 = extractelement <2 x half> %tmp7, i32 0 + br label %bb1 +} + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll index 53a00c240d3..6c27690fb2b 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll @@ -49,9 +49,9 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo(half %src0, half %src } ; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack: -; GFX9: v_mov_b32_e32 v3, 0 -; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 -; GFX9-NEXT: v_mov_b32_e32 v0, v3 +; GFX9: s_waitcnt +; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: s_setpc_b64 define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, half %src2) #0 { %src0.ext = fpext half %src0 to float @@ -66,9 +66,9 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, ha } ; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext: -; GFX9: v_mov_b32_e32 v3, 0 -; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 -; GFX9-NEXT: v_mov_b32_e32 v0, v3 +; GFX9: s_waitcnt +; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: s_setpc_b64 define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src1, half %src2) #0 { %src0.ext = fpext half %src0 to float |
