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-rw-r--r--llvm/lib/Target/Hexagon/Hexagon.td14
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp15
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSubtarget.h5
4 files changed, 20 insertions, 16 deletions
diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td
index 31e08cc1b04..6fa90d9ce62 100644
--- a/llvm/lib/Target/Hexagon/Hexagon.td
+++ b/llvm/lib/Target/Hexagon/Hexagon.td
@@ -54,6 +54,8 @@ def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",
"Support for new-value jumps", [FeaturePackets]>;
def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true",
"Support for new-value stores", [FeaturePackets]>;
+def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true",
+ "Allow GP-relative addressing of global variables">;
def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
"Enable generation of duplex instruction">;
def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
@@ -324,27 +326,27 @@ class Proc<string Name, SchedMachineModel Model,
def : Proc<"hexagonv4", HexagonModelV4,
[ArchV4,
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
- FeaturePackets]>;
+ FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv5", HexagonModelV4,
[ArchV4, ArchV5,
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
- FeaturePackets]>;
+ FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv55", HexagonModelV55,
[ArchV4, ArchV5, ArchV55,
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
- FeaturePackets]>;
+ FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv60", HexagonModelV60,
[ArchV4, ArchV5, ArchV55, ArchV60,
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
- FeaturePackets]>;
+ FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv62", HexagonModelV62,
[ArchV4, ArchV5, ArchV55, ArchV60, ArchV62,
FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
- FeaturePackets]>;
+ FeaturePackets, FeatureSmallData]>;
def : Proc<"hexagonv65", HexagonModelV65,
[ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
- FeatureNVS, FeaturePackets]>;
+ FeatureNVS, FeaturePackets, FeatureSmallData]>;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index fbe8f16bd98..ce42a9bd70f 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1016,7 +1016,7 @@ HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
if (RM == Reloc::Static) {
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
const GlobalObject *GO = GV->getBaseObject();
- if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
+ if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
index 3fe4cc73d2f..c41f0d3c085 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
@@ -60,14 +60,14 @@ INITIALIZE_PASS(HexagonSplitConst32AndConst64, "split-const-for-sdata",
"Hexagon Split Const32s and Const64s", false, false)
bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
- const HexagonTargetObjectFile &TLOF =
- *static_cast<const HexagonTargetObjectFile *>(
- Fn.getTarget().getObjFileLowering());
- if (TLOF.isSmallDataEnabled())
- return true;
+ auto &HST = Fn.getSubtarget<HexagonSubtarget>();
+ auto &HTM = static_cast<const HexagonTargetMachine&>(Fn.getTarget());
+ auto &TLOF = *HTM.getObjFileLowering();
+ if (HST.useSmallData() && TLOF.isSmallDataEnabled())
+ return false;
- const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
- const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
+ const TargetInstrInfo *TII = HST.getInstrInfo();
+ const TargetRegisterInfo *TRI = HST.getRegisterInfo();
// Loop over all of the basic blocks
for (MachineBasicBlock &B : Fn) {
@@ -109,7 +109,6 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
//===----------------------------------------------------------------------===//
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-
FunctionPass *llvm::createHexagonSplitConst32AndConst64() {
return new HexagonSplitConst32AndConst64();
}
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
index b8f7db6ae20..936971fbced 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -55,6 +55,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo {
bool UsePackets = false;
bool UseNewValueJumps = false;
bool UseNewValueStores = false;
+ bool UseSmallData = false;
bool HasMemNoShuf = false;
bool EnableDuplex = false;
@@ -153,10 +154,13 @@ public:
bool hasV65TOpsOnly() const {
return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
}
+
+ bool useLongCalls() const { return UseLongCalls; }
bool useMemops() const { return UseMemops; }
bool usePackets() const { return UsePackets; }
bool useNewValueJumps() const { return UseNewValueJumps; }
bool useNewValueStores() const { return UseNewValueStores; }
+ bool useSmallData() const { return UseSmallData; }
bool modeIEEERndNear() const { return ModeIEEERndNear; }
bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
@@ -165,7 +169,6 @@ public:
bool hasMemNoShuf() const { return HasMemNoShuf; }
bool hasReservedR19() const { return ReservedR19; }
- bool useLongCalls() const { return UseLongCalls; }
bool usePredicatedCalls() const;
bool useBSBScheduling() const { return UseBSBScheduling; }
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