diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/cc.ll | 2 |
2 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index b3d145b2cc4..e9288583884 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -188,11 +188,9 @@ def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; } -// The full condition-code register. This is not modeled fully, but defined -// here primarily, for compatibility with gcc, to allow the inline asm "cc" -// clobber specification to work. +// An alias for "cr0" used by GCC. def CC : PPCReg<"cc">, DwarfRegAlias<CR0> { - let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]; + let Aliases = [CR0]; } // Link register diff --git a/llvm/test/CodeGen/PowerPC/cc.ll b/llvm/test/CodeGen/PowerPC/cc.ll index f92121bd720..c23ee7c9f5c 100644 --- a/llvm/test/CodeGen/PowerPC/cc.ll +++ b/llvm/test/CodeGen/PowerPC/cc.ll @@ -41,7 +41,7 @@ entry: br label %foo foo: - call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc}" (i64 %a) + call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a) br i1 %c, label %bar, label %end bar: |
