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authorJim Grosbach <grosbach@apple.com>2011-08-17 22:57:40 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-17 22:57:40 +0000
commitcbd4ab104b3b8905e2f0f8c376ff9c434483d1a9 (patch)
treefec6b8980c9c0a206f9f3d14a08f73940d2968ac /llvm
parent2b21d86cfe792abee2707b8c44b7a64b79819b9b (diff)
downloadbcm5719-llvm-cbd4ab104b3b8905e2f0f8c376ff9c434483d1a9.tar.gz
bcm5719-llvm-cbd4ab104b3b8905e2f0f8c376ff9c434483d1a9.zip
Thumb assembly parsing and encoding for B.
llvm-svn: 137891
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp4
-rw-r--r--llvm/test/MC/ARM/basic-thumb-instructions.s12
2 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 74d34e14430..f89968f670b 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3035,6 +3035,10 @@ processInstruction(MCInst &Inst,
if (Inst.getOperand(3).getImm() < 8)
Inst.setOpcode(ARM::tADDi3);
break;
+ case ARM::tBcc:
+ // If the conditional is AL, we really want tB.
+ if (Inst.getOperand(1).getImm() == ARMCC::AL)
+ Inst.setOpcode(ARM::tB);
}
}
diff --git a/llvm/test/MC/ARM/basic-thumb-instructions.s b/llvm/test/MC/ARM/basic-thumb-instructions.s
index 7899a550f2a..f690c55b74e 100644
--- a/llvm/test/MC/ARM/basic-thumb-instructions.s
+++ b/llvm/test/MC/ARM/basic-thumb-instructions.s
@@ -76,3 +76,15 @@ _func:
asrs r5, r2
@ CHECK: asrs r5, r2 @ encoding: [0x15,0x41]
+
+
+@------------------------------------------------------------------------------
+@ B
+@------------------------------------------------------------------------------
+ b _baz
+ beq _bar
+
+@ CHECK: b _baz @ encoding: [A,0xe0'A']
+ @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
+@ CHECK: beq _bar @ encoding: [A,0xd0]
+ @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
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