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authorDaniel Sanders <daniel_l_sanders@apple.com>2017-05-17 12:43:30 +0000
committerDaniel Sanders <daniel_l_sanders@apple.com>2017-05-17 12:43:30 +0000
commited205a090db1e6aca740e29a9bb54c589df81f0e (patch)
treed2d19f621371d28ed5ec2826d87c44363995eb17 /llvm/utils/TableGen
parenteafa4aa91023c48c5742b82f8d92841f78c0c4cc (diff)
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[globalisel][tablegen] Require that all registers between instructions of a match are virtual.
Summary: Without this, it's possible to encounter multiple defs for a register. This is triggered by the current version of D32868 when applied to trunk. Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls Reviewed By: qcolombet Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32869 llvm-svn: 303253
Diffstat (limited to 'llvm/utils/TableGen')
-rw-r--r--llvm/utils/TableGen/GlobalISelEmitter.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 2b624d95c66..7a500eaf411 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -775,6 +775,8 @@ public:
void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule,
StringRef OperandExpr) const override {
OS << "if (!" << OperandExpr + ".isReg())\n"
+ << " return false;\n"
+ << "if (TRI.isPhysicalRegister(" << OperandExpr + ".getReg()))\n"
<< " return false;\n";
std::string InsnVarName = Rule.defineInsnVar(
OS, *InsnMatcher,
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