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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-05-17 12:43:30 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-05-17 12:43:30 +0000 |
| commit | ed205a090db1e6aca740e29a9bb54c589df81f0e (patch) | |
| tree | d2d19f621371d28ed5ec2826d87c44363995eb17 | |
| parent | eafa4aa91023c48c5742b82f8d92841f78c0c4cc (diff) | |
| download | bcm5719-llvm-ed205a090db1e6aca740e29a9bb54c589df81f0e.tar.gz bcm5719-llvm-ed205a090db1e6aca740e29a9bb54c589df81f0e.zip | |
[globalisel][tablegen] Require that all registers between instructions of a match are virtual.
Summary:
Without this, it's possible to encounter multiple defs for a register.
This is triggered by the current version of D32868 when applied to trunk.
Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls
Reviewed By: qcolombet
Subscribers: llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D32869
llvm-svn: 303253
| -rw-r--r-- | llvm/test/TableGen/GlobalISelEmitter.td | 4 | ||||
| -rw-r--r-- | llvm/utils/TableGen/GlobalISelEmitter.cpp | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td index eb0609c5126..aeac85962f6 100644 --- a/llvm/test/TableGen/GlobalISelEmitter.td +++ b/llvm/test/TableGen/GlobalISelEmitter.td @@ -138,6 +138,8 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), // CHECK-NEXT: return false; // CHECK-NEXT: if (!MI0.getOperand(1).isReg()) // CHECK-NEXT: return false; +// CHECK-NEXT: if (TRI.isPhysicalRegister(MI0.getOperand(1).getReg())) +// CHECK-NEXT: return false; // CHECK-NEXT: MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(1).getReg()); // CHECK-NEXT: if (MI1.getNumOperands() < 3) // CHECK-NEXT: return false; @@ -180,6 +182,8 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), // CHECK-NEXT: return false; // CHECK-NEXT: if (!MI0.getOperand(2).isReg()) // CHECK-NEXT: return false; +// CHECK-NEXT: if (TRI.isPhysicalRegister(MI0.getOperand(2).getReg())) +// CHECK-NEXT: return false; // CHECK-NEXT: MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(2).getReg()); // CHECK-NEXT: if (MI1.getNumOperands() < 3) // CHECK-NEXT: return false; diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index 2b624d95c66..7a500eaf411 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -775,6 +775,8 @@ public: void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule, StringRef OperandExpr) const override { OS << "if (!" << OperandExpr + ".isReg())\n" + << " return false;\n" + << "if (TRI.isPhysicalRegister(" << OperandExpr + ".getReg()))\n" << " return false;\n"; std::string InsnVarName = Rule.defineInsnVar( OS, *InsnMatcher, |
