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authorCraig Topper <craig.topper@intel.com>2018-01-16 06:07:16 +0000
committerCraig Topper <craig.topper@intel.com>2018-01-16 06:07:16 +0000
commit7a0c601f95fcf07346c295298671d439e88e9ef6 (patch)
tree246fedf598540d86f1323a1d3eba458dc035eae5 /llvm/utils/TableGen/X86RecognizableInstr.cpp
parentdaa385f480c640599f1983fec6f203752f9c05e3 (diff)
downloadbcm5719-llvm-7a0c601f95fcf07346c295298671d439e88e9ef6.tar.gz
bcm5719-llvm-7a0c601f95fcf07346c295298671d439e88e9ef6.zip
[X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode using the 0x90 encoding in 64-bit mode.
Prior to this we had a separate instruction and register class that excluded eax to prevent matching the instruction that would encode with 0x90. This patch changes this to just use an InstAlias to force xchgl %eax, %eax to use XCHG32rr instruction in 64-bit mode. This gets rid of the separate instruction and register class. llvm-svn: 322532
Diffstat (limited to 'llvm/utils/TableGen/X86RecognizableInstr.cpp')
-rw-r--r--llvm/utils/TableGen/X86RecognizableInstr.cpp2
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 9afdd7e0963..81cd12f92a5 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -927,7 +927,6 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("VK32WM", TYPE_VK)
TYPE("VK64", TYPE_VK)
TYPE("VK64WM", TYPE_VK)
- TYPE("GR32_NOAX", TYPE_Rv)
TYPE("vx64mem", TYPE_MVSIBX)
TYPE("vx128mem", TYPE_MVSIBX)
TYPE("vx256mem", TYPE_MVSIBX)
@@ -1195,7 +1194,6 @@ RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
ENCODING("GR64", ENCODING_RO)
ENCODING("GR16", ENCODING_Rv)
ENCODING("GR8", ENCODING_RB)
- ENCODING("GR32_NOAX", ENCODING_Rv)
errs() << "Unhandled opcode modifier encoding " << s << "\n";
llvm_unreachable("Unhandled opcode modifier encoding");
}
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