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| author | Craig Topper <craig.topper@gmail.com> | 2015-01-06 08:59:30 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2015-01-06 08:59:30 +0000 |
| commit | 639445494faeeb78db80434c65a0aa0f5a649f2d (patch) | |
| tree | 5a2d949883b4b191ae194896457b8c4be76eba03 /llvm/utils/TableGen/X86RecognizableInstr.cpp | |
| parent | 9b6b8228148c88d41c098005133eeea1e1005162 (diff) | |
| download | bcm5719-llvm-639445494faeeb78db80434c65a0aa0f5a649f2d.tar.gz bcm5719-llvm-639445494faeeb78db80434c65a0aa0f5a649f2d.zip | |
[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.
Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building.
llvm-svn: 225256
Diffstat (limited to 'llvm/utils/TableGen/X86RecognizableInstr.cpp')
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 1ee376e103c..9351fcb0fec 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -956,7 +956,8 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("SSECC", TYPE_IMM3) TYPE("AVXCC", TYPE_IMM5) TYPE("AVX512RC", TYPE_IMM32) - TYPE("brtarget", TYPE_RELv) + TYPE("brtarget32", TYPE_RELv) + TYPE("brtarget16", TYPE_RELv) TYPE("brtarget8", TYPE_REL8) TYPE("f80mem", TYPE_M80FP) TYPE("lea32mem", TYPE_LEA) @@ -1212,7 +1213,8 @@ RecognizableInstr::relocationEncodingFromString(const std::string &s, ENCODING("i64i32imm_pcrel", ENCODING_ID) ENCODING("i16imm_pcrel", ENCODING_IW) ENCODING("i32imm_pcrel", ENCODING_ID) - ENCODING("brtarget", ENCODING_Iv) + ENCODING("brtarget32", ENCODING_Iv) + ENCODING("brtarget16", ENCODING_Iv) ENCODING("brtarget8", ENCODING_IB) ENCODING("i64imm", ENCODING_IO) ENCODING("offset16_8", ENCODING_Ia) |
