From d37dc77b6e52d46f2388070f2fd530424b49a8cd Mon Sep 17 00:00:00 2001 From: Geoff Berry Date: Mon, 29 Jan 2018 18:47:48 +0000 Subject: [AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs Summary: Fix a few places that were modifying code after register allocation to set the renamable bit correctly to avoid failing the validation added in D42449. llvm-svn: 323675 --- llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/test') diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir index 85ce251ac31..9939fa61820 100644 --- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir +++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir @@ -40,7 +40,7 @@ stack: constants: body: | bb.0.entry: - renamable %zero = SLL_MMR6 killed renamable %zero, 0 + %zero = SLL_MMR6 killed %zero, 0 JRC16_MM undef %ra, implicit %v0 ... -- cgit v1.2.3