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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2015-02-16 21:50:56 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2015-02-16 21:50:56 +0000 |
| commit | b2c00f3286cdde6bf7c5ac100d1a5d143e3cb098 (patch) | |
| tree | d0bd27029197166c90945509d5ed5bdf1758ccde /llvm/test | |
| parent | 3e0023b8f6277b4b1335214bdf5ea4a76005fe33 (diff) | |
| download | bcm5719-llvm-b2c00f3286cdde6bf7c5ac100d1a5d143e3cb098.tar.gz bcm5719-llvm-b2c00f3286cdde6bf7c5ac100d1a5d143e3cb098.zip | |
[X86][SSE] Add SSE MOVQ instructions to SSEPackedInt domain
Patch to explicitly add the SSE MOVQ (rr,mr,rm) instructions to SSEPackedInt domain - prevents a number of costly domain switches.
Differential Revision: http://reviews.llvm.org/D7600
llvm-svn: 229439
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-or.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-mmx.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/widen_load-1.ll | 4 |
4 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll b/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll index 222068dc579..7eaa5bb7e88 100644 --- a/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll +++ b/llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll @@ -26,7 +26,7 @@ entry: } ; CHECK-LABEL: zero_test -; CHECK: xorps %xmm0, %xmm0 +; CHECK: pxor %xmm0, %xmm0 ; CHECK: ret define void @zero_test() { diff --git a/llvm/test/CodeGen/X86/combine-or.ll b/llvm/test/CodeGen/X86/combine-or.ll index f9e917a937c..8a0ffc128e5 100644 --- a/llvm/test/CodeGen/X86/combine-or.ll +++ b/llvm/test/CodeGen/X86/combine-or.ll @@ -255,7 +255,7 @@ define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: test20: ; CHECK: # BB#0: -; CHECK-NEXT: orps %xmm1, %xmm0 +; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero ; CHECK-NEXT: retq %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2> diff --git a/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll b/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll index 4ecba565e9c..2e0c67b1642 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-mmx.ll @@ -54,7 +54,7 @@ define void @test1() { ; ; X64-LABEL: test1: ; X64: ## BB#0: ## %entry -; X64-NEXT: xorps %xmm0, %xmm0 +; X64-NEXT: pxor %xmm0, %xmm0 ; X64-NEXT: movq %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %mm0 ; X64-NEXT: pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7] diff --git a/llvm/test/CodeGen/X86/widen_load-1.ll b/llvm/test/CodeGen/X86/widen_load-1.ll index c59cc58f40f..613742427ef 100644 --- a/llvm/test/CodeGen/X86/widen_load-1.ll +++ b/llvm/test/CodeGen/X86/widen_load-1.ll @@ -9,8 +9,8 @@ ; SSE: movaps %xmm0, (%rsp) ; SSE: callq killcommon -; AVX: vmovaps compl+128(%rip), %xmm0 -; AVX: vmovaps %xmm0, (%rsp) +; AVX: vmovdqa compl+128(%rip), %xmm0 +; AVX: vmovdqa %xmm0, (%rsp) ; AVX: callq killcommon @compl = linkonce global [20 x i64] zeroinitializer, align 64 ; <[20 x i64]*> [#uses=1] |
