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| author | Evandro Menezes <e.menezes@samsung.com> | 2018-12-10 17:17:26 +0000 |
|---|---|---|
| committer | Evandro Menezes <e.menezes@samsung.com> | 2018-12-10 17:17:26 +0000 |
| commit | 53f0d41dc4879cf79bea8acc4aa87064a085d05c (patch) | |
| tree | fcd51f1cc7987782599adb5389f6780616b9f263 /llvm/test/tools/llvm-mca | |
| parent | 1f6b247717c99678dceb06faf1e4c01b758f3e2e (diff) | |
| download | bcm5719-llvm-53f0d41dc4879cf79bea8acc4aa87064a085d05c.tar.gz bcm5719-llvm-53f0d41dc4879cf79bea8acc4aa87064a085d05c.zip | |
[AArch64] Refactor the Exynos scheduling predicates
Refactor the scheduling predicates based on `MCInstPredicate`. In this
case, for the Exynos processors.
Differential revision: https://reviews.llvm.org/D55345
llvm-svn: 348774
Diffstat (limited to 'llvm/test/tools/llvm-mca')
3 files changed, 47 insertions, 50 deletions
diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s index 58fb4f0afeb..c580a8db2be 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s +++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s @@ -3,31 +3,31 @@ # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3 sub w0, w1, w2, sxtb #0 - add w3, w4, w5, sxth #1 + add x3, x4, w5, sxth #1 subs x6, x7, w8, uxtw #2 adds x9, x10, x11, uxtx #3 sub w12, w13, w14, uxtb #3 - add w15, w16, w17, uxth #2 + add x15, x16, w17, uxth #2 subs x18, x19, w20, sxtw #1 adds x21, x22, x23, sxtx #0 # ALL: Iterations: 100 # ALL-NEXT: Instructions: 800 -# EM1-NEXT: Total Cycles: 537 -# EM3-NEXT: Total Cycles: 403 +# EM1-NEXT: Total Cycles: 403 +# EM3-NEXT: Total Cycles: 303 # ALL-NEXT: Total uOps: 800 # EM1: Dispatch Width: 4 -# EM1-NEXT: uOps Per Cycle: 1.49 -# EM1-NEXT: IPC: 1.49 -# EM1-NEXT: Block RThroughput: 5.3 +# EM1-NEXT: uOps Per Cycle: 1.99 +# EM1-NEXT: IPC: 1.99 +# EM1-NEXT: Block RThroughput: 4.0 # EM3: Dispatch Width: 6 -# EM3-NEXT: uOps Per Cycle: 1.99 -# EM3-NEXT: IPC: 1.99 -# EM3-NEXT: Block RThroughput: 4.0 +# EM3-NEXT: uOps Per Cycle: 2.64 +# EM3-NEXT: IPC: 2.64 +# EM3-NEXT: Block RThroughput: 3.0 # ALL: Instruction Info: # ALL-NEXT: [1]: #uOps @@ -39,20 +39,20 @@ # ALL: [1] [2] [3] [4] [5] [6] Instructions: -# EM1-NEXT: 1 2 0.67 sub w0, w1, w2, sxtb -# EM1-NEXT: 1 2 0.67 add w3, w4, w5, sxth #1 -# EM1-NEXT: 1 2 0.67 subs x6, x7, w8, uxtw #2 -# EM1-NEXT: 1 2 0.67 adds x9, x10, x11, uxtx #3 +# EM1-NEXT: 1 1 0.33 sub w0, w1, w2, sxtb +# EM1-NEXT: 1 2 0.67 add x3, x4, w5, sxth #1 +# EM1-NEXT: 1 1 0.33 subs x6, x7, w8, uxtw #2 +# EM1-NEXT: 1 1 0.33 adds x9, x10, x11, uxtx #3 # EM1-NEXT: 1 2 0.67 sub w12, w13, w14, uxtb #3 -# EM1-NEXT: 1 2 0.67 add w15, w16, w17, uxth #2 +# EM1-NEXT: 1 2 0.67 add x15, x16, w17, uxth #2 # EM1-NEXT: 1 2 0.67 subs x18, x19, w20, sxtw #1 -# EM1-NEXT: 1 2 0.67 adds x21, x22, x23, sxtx +# EM1-NEXT: 1 1 0.33 adds x21, x22, x23, sxtx -# EM3-NEXT: 1 2 0.50 sub w0, w1, w2, sxtb -# EM3-NEXT: 1 2 0.50 add w3, w4, w5, sxth #1 -# EM3-NEXT: 1 2 0.50 subs x6, x7, w8, uxtw #2 -# EM3-NEXT: 1 2 0.50 adds x9, x10, x11, uxtx #3 +# EM3-NEXT: 1 1 0.25 sub w0, w1, w2, sxtb +# EM3-NEXT: 1 2 0.50 add x3, x4, w5, sxth #1 +# EM3-NEXT: 1 1 0.25 subs x6, x7, w8, uxtw #2 +# EM3-NEXT: 1 1 0.25 adds x9, x10, x11, uxtx #3 # EM3-NEXT: 1 2 0.50 sub w12, w13, w14, uxtb #3 -# EM3-NEXT: 1 2 0.50 add w15, w16, w17, uxth #2 +# EM3-NEXT: 1 2 0.50 add x15, x16, w17, uxth #2 # EM3-NEXT: 1 2 0.50 subs x18, x19, w20, sxtw #1 -# EM3-NEXT: 1 2 0.50 adds x21, x22, x23, sxtx +# EM3-NEXT: 1 1 0.25 adds x21, x22, x23, sxtx diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/register-offset.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/register-offset.s index fe1c75e234f..b31b3966829 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Exynos/register-offset.s +++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/register-offset.s @@ -9,20 +9,17 @@ # ALL: Iterations: 100 # ALL-NEXT: Instructions: 400 - -# EM1-NEXT: Total Cycles: 408 -# EM3-NEXT: Total Cycles: 208 - -# ALL-NEXT: Total uOps: 800 +# ALL-NEXT: Total Cycles: 308 +# ALL-NEXT: Total uOps: 600 # EM1: Dispatch Width: 4 -# EM1-NEXT: uOps Per Cycle: 1.96 -# EM1-NEXT: IPC: 0.98 +# EM1-NEXT: uOps Per Cycle: 1.95 +# EM1-NEXT: IPC: 1.30 # EM1-NEXT: Block RThroughput: 2.0 # EM3: Dispatch Width: 6 -# EM3-NEXT: uOps Per Cycle: 3.85 -# EM3-NEXT: IPC: 1.92 +# EM3-NEXT: uOps Per Cycle: 1.95 +# EM3-NEXT: IPC: 1.30 # EM3-NEXT: Block RThroughput: 2.0 # ALL: Instruction Info: @@ -35,12 +32,12 @@ # ALL: [1] [2] [3] [4] [5] [6] Instructions: -# EM1-NEXT: 2 5 1.00 * ldr w0, [x1, x2] -# EM1-NEXT: 2 2 1.00 * str x3, [x4, w5, sxtw] -# EM1-NEXT: 2 5 1.00 * ldr x6, [x7, w8, uxtw #3] -# EM1-NEXT: 2 2 1.00 * str x9, [x10, x11, lsl #3] +# EM1-NEXT: 1 5 1.00 * ldr w0, [x1, x2] +# EM3-NEXT: 1 5 0.50 * ldr w0, [x1, x2] -# EM3-NEXT: 2 5 0.50 * ldr w0, [x1, x2] -# EM3-NEXT: 2 1 1.00 * str x3, [x4, w5, sxtw] +# ALL-NEXT: 2 2 1.00 * str x3, [x4, w5, sxtw] + +# EM1-NEXT: 2 5 1.00 * ldr x6, [x7, w8, uxtw #3] # EM3-NEXT: 2 5 0.50 * ldr x6, [x7, w8, uxtw #3] -# EM3-NEXT: 2 1 1.00 * str x9, [x10, x11, lsl #3] + +# ALL-NEXT: 1 1 1.00 * str x9, [x10, x11, lsl #3] diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s index 4b73836dc67..e37d2d09f2a 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s +++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s @@ -10,20 +10,20 @@ # ALL: Iterations: 100 # ALL-NEXT: Instructions: 400 -# EM1-NEXT: Total Cycles: 271 -# EM3-NEXT: Total Cycles: 203 +# EM1-NEXT: Total Cycles: 204 +# EM3-NEXT: Total Cycles: 154 # ALL-NEXT: Total uOps: 400 # EM1: Dispatch Width: 4 -# EM1-NEXT: uOps Per Cycle: 1.48 -# EM1-NEXT: IPC: 1.48 -# EM1-NEXT: Block RThroughput: 2.7 +# EM1-NEXT: uOps Per Cycle: 1.96 +# EM1-NEXT: IPC: 1.96 +# EM1-NEXT: Block RThroughput: 2.0 # EM3: Dispatch Width: 6 -# EM3-NEXT: uOps Per Cycle: 1.97 -# EM3-NEXT: IPC: 1.97 -# EM3-NEXT: Block RThroughput: 2.0 +# EM3-NEXT: uOps Per Cycle: 2.60 +# EM3-NEXT: IPC: 2.60 +# EM3-NEXT: Block RThroughput: 1.5 # ALL: Instruction Info: # ALL-NEXT: [1]: #uOps @@ -35,12 +35,12 @@ # ALL: [1] [2] [3] [4] [5] [6] Instructions: -# EM1-NEXT: 1 2 0.67 add w0, w1, w2 +# EM1-NEXT: 1 1 0.33 add w0, w1, w2 # EM1-NEXT: 1 2 0.67 sub x3, x4, x5, lsr #1 -# EM1-NEXT: 1 2 0.67 adds x6, x7, x8, lsl #2 +# EM1-NEXT: 1 1 0.33 adds x6, x7, x8, lsl #2 # EM1-NEXT: 1 2 0.67 subs w9, w10, w11, asr #3 -# EM3-NEXT: 1 2 0.50 add w0, w1, w2 +# EM3-NEXT: 1 1 0.25 add w0, w1, w2 # EM3-NEXT: 1 2 0.50 sub x3, x4, x5, lsr #1 -# EM3-NEXT: 1 2 0.50 adds x6, x7, x8, lsl #2 +# EM3-NEXT: 1 1 0.25 adds x6, x7, x8, lsl #2 # EM3-NEXT: 1 2 0.50 subs w9, w10, w11, asr #3 |
