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authorSanjay Patel <spatel@rotateright.com>2017-07-15 15:29:47 +0000
committerSanjay Patel <spatel@rotateright.com>2017-07-15 15:29:47 +0000
commit55b9f88ecc4420abf728c0563c6791d35972240f (patch)
treec1592486fde696bf40056d3bfed3e593156ba452 /llvm/test/Transforms
parentd994e3f35db28378171115855070ca821c7c3160 (diff)
downloadbcm5719-llvm-55b9f88ecc4420abf728c0563c6791d35972240f.tar.gz
bcm5719-llvm-55b9f88ecc4420abf728c0563c6791d35972240f.zip
[InstCombine] allow (0 - x) & 1 --> x & 1 for vectors
llvm-svn: 308098
Diffstat (limited to 'llvm/test/Transforms')
-rw-r--r--llvm/test/Transforms/InstCombine/and2.ll3
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/test/Transforms/InstCombine/and2.ll b/llvm/test/Transforms/InstCombine/and2.ll
index 001ac58891e..9b3bbfe4920 100644
--- a/llvm/test/Transforms/InstCombine/and2.ll
+++ b/llvm/test/Transforms/InstCombine/and2.ll
@@ -98,8 +98,7 @@ define i64 @test9(i64 %x) {
; combine -x & 1 into x & 1
define <2 x i64> @test9vec(<2 x i64> %x) {
; CHECK-LABEL: @test9vec(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i64> zeroinitializer, [[X:%.*]]
-; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> [[SUB]], <i64 1, i64 1>
+; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> %x, <i64 1, i64 1>
; CHECK-NEXT: ret <2 x i64> [[AND]]
;
%sub = sub nsw <2 x i64> <i64 0, i64 0>, %x
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