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author | Sanjay Patel <spatel@rotateright.com> | 2016-06-02 20:01:37 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2016-06-02 20:01:37 +0000 |
commit | dba8b4c04d579b946572800d20419e70177b3194 (patch) | |
tree | e5e683c188b16a381030fc74d498b32cee96c050 /llvm/test/Transforms/InstCombine/fabs.ll | |
parent | 617409f0c0a990d2d4b62f1a3e02ca26bc41d67a (diff) | |
download | bcm5719-llvm-dba8b4c04d579b946572800d20419e70177b3194.tar.gz bcm5719-llvm-dba8b4c04d579b946572800d20419e70177b3194.zip |
transform obscured FP sign bit ops into a fabs/fneg using TLI hook
This is effectively a revert of:
http://reviews.llvm.org/rL249702 - [InstCombine] transform masking off of an FP sign bit into a fabs() intrinsic call (PR24886)
and:
http://reviews.llvm.org/rL249701 - [ValueTracking] teach computeKnownBits that a fabs() clears sign bits
and a reimplementation as a DAG combine for targets that have IEEE754-compliant fabs/fneg instructions.
This is intended to resolve the objections raised on the dev list:
http://lists.llvm.org/pipermail/llvm-dev/2016-April/098154.html
and:
https://llvm.org/bugs/show_bug.cgi?id=24886#c4
In the interest of patch minimalism, I've only partly enabled AArch64. PowerPC, MIPS, x86 and others can enable later.
Differential Revision: http://reviews.llvm.org/D19391
llvm-svn: 271573
Diffstat (limited to 'llvm/test/Transforms/InstCombine/fabs.ll')
-rw-r--r-- | llvm/test/Transforms/InstCombine/fabs.ll | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/llvm/test/Transforms/InstCombine/fabs.ll b/llvm/test/Transforms/InstCombine/fabs.ll index 941270df0e9..0479549bea3 100644 --- a/llvm/test/Transforms/InstCombine/fabs.ll +++ b/llvm/test/Transforms/InstCombine/fabs.ll @@ -41,7 +41,6 @@ define fp128 @square_fabs_call_f128(fp128 %x) { declare float @llvm.fabs.f32(float) declare double @llvm.fabs.f64(double) declare fp128 @llvm.fabs.f128(fp128) -declare <4 x float> @llvm.fabs.v4f32(<4 x float>) define float @square_fabs_intrinsic_f32(float %x) { %mul = fmul float %x, %x @@ -99,27 +98,3 @@ define float @square_fabs_shrink_call2(float %x) { ; CHECK-NEXT: ret float %sq } -; A scalar fabs op makes the sign bit zero, so masking off all of the other bits means we can return zero. - -define i32 @fabs_value_tracking_f32(float %x) { - %call = call float @llvm.fabs.f32(float %x) - %bc = bitcast float %call to i32 - %and = and i32 %bc, 2147483648 - ret i32 %and - -; CHECK-LABEL: fabs_value_tracking_f32( -; CHECK: ret i32 0 -} - -; TODO: A vector fabs op makes the sign bits zero, so masking off all of the other bits means we can return zero. - -define <4 x i32> @fabs_value_tracking_v4f32(<4 x float> %x) { - %call = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x) - %bc = bitcast <4 x float> %call to <4 x i32> - %and = and <4 x i32> %bc, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648> - ret <4 x i32> %and - -; CHECK-LABEL: fabs_value_tracking_v4f32( -; CHECK: ret <4 x i32> %and -} - |