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authorSanjay Patel <spatel@rotateright.com>2016-06-02 20:01:37 +0000
committerSanjay Patel <spatel@rotateright.com>2016-06-02 20:01:37 +0000
commitdba8b4c04d579b946572800d20419e70177b3194 (patch)
treee5e683c188b16a381030fc74d498b32cee96c050 /llvm/test
parent617409f0c0a990d2d4b62f1a3e02ca26bc41d67a (diff)
downloadbcm5719-llvm-dba8b4c04d579b946572800d20419e70177b3194.tar.gz
bcm5719-llvm-dba8b4c04d579b946572800d20419e70177b3194.zip
transform obscured FP sign bit ops into a fabs/fneg using TLI hook
This is effectively a revert of: http://reviews.llvm.org/rL249702 - [InstCombine] transform masking off of an FP sign bit into a fabs() intrinsic call (PR24886) and: http://reviews.llvm.org/rL249701 - [ValueTracking] teach computeKnownBits that a fabs() clears sign bits and a reimplementation as a DAG combine for targets that have IEEE754-compliant fabs/fneg instructions. This is intended to resolve the objections raised on the dev list: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098154.html and: https://llvm.org/bugs/show_bug.cgi?id=24886#c4 In the interest of patch minimalism, I've only partly enabled AArch64. PowerPC, MIPS, x86 and others can enable later. Differential Revision: http://reviews.llvm.org/D19391 llvm-svn: 271573
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AArch64/fcvt-int.ll8
-rw-r--r--llvm/test/Transforms/InstCombine/and2.ll42
-rw-r--r--llvm/test/Transforms/InstCombine/fabs.ll25
3 files changed, 2 insertions, 73 deletions
diff --git a/llvm/test/CodeGen/AArch64/fcvt-int.ll b/llvm/test/CodeGen/AArch64/fcvt-int.ll
index 9092bea8c2a..e52b601b145 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-int.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-int.ll
@@ -153,9 +153,7 @@ define double @test_bitcasti64todouble(i64 %in) {
define double @bitcast_fabs(double %x) {
; CHECK-LABEL: bitcast_fabs:
; CHECK: ; BB#0:
-; CHECK-NEXT: fmov x8, d0
-; CHECK-NEXT: and x8, x8, #0x7fffffffffffffff
-; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: fabs d0, d0
; CHECK-NEXT: ret
;
%bc1 = bitcast double %x to i64
@@ -167,9 +165,7 @@ define double @bitcast_fabs(double %x) {
define float @bitcast_fneg(float %x) {
; CHECK-LABEL: bitcast_fneg:
; CHECK: ; BB#0:
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: eor w8, w8, #0x80000000
-; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: fneg s0, s0
; CHECK-NEXT: ret
;
%bc1 = bitcast float %x to i32
diff --git a/llvm/test/Transforms/InstCombine/and2.ll b/llvm/test/Transforms/InstCombine/and2.ll
index 326bfda3855..7a0a9d88407 100644
--- a/llvm/test/Transforms/InstCombine/and2.ll
+++ b/llvm/test/Transforms/InstCombine/and2.ll
@@ -103,45 +103,3 @@ define i64 @test10(i64 %x) {
ret i64 %add
}
-define i64 @fabs_double(double %x) {
-; CHECK-LABEL: @fabs_double(
-; CHECK-NEXT: %fabs = call double @llvm.fabs.f64(double %x)
-; CHECK-NEXT: %and = bitcast double %fabs to i64
-; CHECK-NEXT: ret i64 %and
- %bc = bitcast double %x to i64
- %and = and i64 %bc, 9223372036854775807
- ret i64 %and
-}
-
-define i64 @fabs_double_swap(double %x) {
-; CHECK-LABEL: @fabs_double_swap(
-; CHECK-NEXT: %fabs = call double @llvm.fabs.f64(double %x)
-; CHECK-NEXT: %and = bitcast double %fabs to i64
-; CHECK-NEXT: ret i64 %and
- %bc = bitcast double %x to i64
- %and = and i64 9223372036854775807, %bc
- ret i64 %and
-}
-
-define i32 @fabs_float(float %x) {
-; CHECK-LABEL: @fabs_float(
-; CHECK-NEXT: %fabs = call float @llvm.fabs.f32(float %x)
-; CHECK-NEXT: %and = bitcast float %fabs to i32
-; CHECK-NEXT: ret i32 %and
- %bc = bitcast float %x to i32
- %and = and i32 %bc, 2147483647
- ret i32 %and
-}
-
-; Make sure that only a bitcast is transformed.
-
-define i64 @fabs_double_not_bitcast(double %x) {
-; CHECK-LABEL: @fabs_double_not_bitcast(
-; CHECK-NEXT: %bc = fptoui double %x to i64
-; CHECK-NEXT: %and = and i64 %bc, 9223372036854775807
-; CHECK-NEXT: ret i64 %and
- %bc = fptoui double %x to i64
- %and = and i64 %bc, 9223372036854775807
- ret i64 %and
-}
-
diff --git a/llvm/test/Transforms/InstCombine/fabs.ll b/llvm/test/Transforms/InstCombine/fabs.ll
index 941270df0e9..0479549bea3 100644
--- a/llvm/test/Transforms/InstCombine/fabs.ll
+++ b/llvm/test/Transforms/InstCombine/fabs.ll
@@ -41,7 +41,6 @@ define fp128 @square_fabs_call_f128(fp128 %x) {
declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)
declare fp128 @llvm.fabs.f128(fp128)
-declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
define float @square_fabs_intrinsic_f32(float %x) {
%mul = fmul float %x, %x
@@ -99,27 +98,3 @@ define float @square_fabs_shrink_call2(float %x) {
; CHECK-NEXT: ret float %sq
}
-; A scalar fabs op makes the sign bit zero, so masking off all of the other bits means we can return zero.
-
-define i32 @fabs_value_tracking_f32(float %x) {
- %call = call float @llvm.fabs.f32(float %x)
- %bc = bitcast float %call to i32
- %and = and i32 %bc, 2147483648
- ret i32 %and
-
-; CHECK-LABEL: fabs_value_tracking_f32(
-; CHECK: ret i32 0
-}
-
-; TODO: A vector fabs op makes the sign bits zero, so masking off all of the other bits means we can return zero.
-
-define <4 x i32> @fabs_value_tracking_v4f32(<4 x float> %x) {
- %call = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
- %bc = bitcast <4 x float> %call to <4 x i32>
- %and = and <4 x i32> %bc, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
- ret <4 x i32> %and
-
-; CHECK-LABEL: fabs_value_tracking_v4f32(
-; CHECK: ret <4 x i32> %and
-}
-
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