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| author | Marina Yatsina <marina.yatsina@intel.com> | 2016-01-19 15:37:56 +0000 |
|---|---|---|
| committer | Marina Yatsina <marina.yatsina@intel.com> | 2016-01-19 15:37:56 +0000 |
| commit | b9f4f62cfe15dd6dc2c827c6cc9c51f72f933c5c (patch) | |
| tree | d714ae4d0361b0a733cae932cb9af859b942340f /llvm/test/MC/X86/index-operations.s | |
| parent | b5d539380a9b548f28ffa067067f90d3139ca767 (diff) | |
| download | bcm5719-llvm-b9f4f62cfe15dd6dc2c827c6cc9c51f72f933c5c.tar.gz bcm5719-llvm-b9f4f62cfe15dd6dc2c827c6cc9c51f72f933c5c.zip | |
[X86] Adding support for missing variations of X86 string related instructions
The following are legal according to X86 spec:
ins mem, DX
outs DX, mem
lods mem
stos mem
scas mem
cmps mem, mem
movs mem, mem
Differential Revision: http://reviews.llvm.org/D14827
llvm-svn: 258132
Diffstat (limited to 'llvm/test/MC/X86/index-operations.s')
| -rw-r--r-- | llvm/test/MC/X86/index-operations.s | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/test/MC/X86/index-operations.s b/llvm/test/MC/X86/index-operations.s index 9f69b0b7849..0f9bc91f7ad 100644 --- a/llvm/test/MC/X86/index-operations.s +++ b/llvm/test/MC/X86/index-operations.s @@ -144,3 +144,19 @@ insw %dx, (%edi) // 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d] // 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d] // 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d] + +insw %dx, (%bx) +// ERR64: invalid 16-bit base register +// 32: insw %dx, %es:(%di) # encoding: [0x66,0x67,0x6d] +// 16: insw %dx, %es:(%di) # encoding: [0x6d] + +insw %dx, (%ebx) +// 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d] +// 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d] +// 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d] + +insw %dx, (%rbx) +// 64: insw %dx, %es:(%rdi) # encoding: [0x66,0x6d] +// ERR32: 64-bit +// ERR16: 64-bit + |
