From b9f4f62cfe15dd6dc2c827c6cc9c51f72f933c5c Mon Sep 17 00:00:00 2001 From: Marina Yatsina Date: Tue, 19 Jan 2016 15:37:56 +0000 Subject: [X86] Adding support for missing variations of X86 string related instructions The following are legal according to X86 spec: ins mem, DX outs DX, mem lods mem stos mem scas mem cmps mem, mem movs mem, mem Differential Revision: http://reviews.llvm.org/D14827 llvm-svn: 258132 --- llvm/test/MC/X86/index-operations.s | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'llvm/test/MC/X86/index-operations.s') diff --git a/llvm/test/MC/X86/index-operations.s b/llvm/test/MC/X86/index-operations.s index 9f69b0b7849..0f9bc91f7ad 100644 --- a/llvm/test/MC/X86/index-operations.s +++ b/llvm/test/MC/X86/index-operations.s @@ -144,3 +144,19 @@ insw %dx, (%edi) // 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d] // 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d] // 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d] + +insw %dx, (%bx) +// ERR64: invalid 16-bit base register +// 32: insw %dx, %es:(%di) # encoding: [0x66,0x67,0x6d] +// 16: insw %dx, %es:(%di) # encoding: [0x6d] + +insw %dx, (%ebx) +// 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d] +// 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d] +// 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d] + +insw %dx, (%rbx) +// 64: insw %dx, %es:(%rdi) # encoding: [0x66,0x6d] +// ERR32: 64-bit +// ERR16: 64-bit + -- cgit v1.2.3