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| author | Mandeep Singh Grang <mgrang@codeaurora.org> | 2018-05-17 17:31:27 +0000 |
|---|---|---|
| committer | Mandeep Singh Grang <mgrang@codeaurora.org> | 2018-05-17 17:31:27 +0000 |
| commit | ef0ebf2806b57e73bdd93f8ffffde164dda6e68c (patch) | |
| tree | 24d0fc38af584dac47af8d33940699be175fc389 /llvm/test/MC/RISCV | |
| parent | 6dcea6d28fe1e8257de84595392dc9f321b68dfa (diff) | |
| download | bcm5719-llvm-ef0ebf2806b57e73bdd93f8ffffde164dda6e68c.tar.gz bcm5719-llvm-ef0ebf2806b57e73bdd93f8ffffde164dda6e68c.zip | |
[RISCV] Implement MC layer support for the tail pseudoinstruction
Summary:
This patch implements MC support for tail psuedo instruction.
A follow-up patch implements the codegen support as well as handling of the indirect tail pseudo instruction.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, llvm-commits
Differential Revision: https://reviews.llvm.org/D46221
llvm-svn: 332634
Diffstat (limited to 'llvm/test/MC/RISCV')
| -rw-r--r-- | llvm/test/MC/RISCV/tail-call-invalid.s | 12 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/tail-call.s | 47 |
2 files changed, 59 insertions, 0 deletions
diff --git a/llvm/test/MC/RISCV/tail-call-invalid.s b/llvm/test/MC/RISCV/tail-call-invalid.s new file mode 100644 index 00000000000..270d84df58a --- /dev/null +++ b/llvm/test/MC/RISCV/tail-call-invalid.s @@ -0,0 +1,12 @@ +# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s + +tail 1234 # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name +tail %pcrel_hi(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name +tail %pcrel_lo(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name +tail %pcrel_hi(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name +tail %pcrel_lo(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name +tail %hi(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name +tail %lo(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name +tail %hi(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name +tail %lo(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name diff --git a/llvm/test/MC/RISCV/tail-call.s b/llvm/test/MC/RISCV/tail-call.s new file mode 100644 index 00000000000..dcbe57933a9 --- /dev/null +++ b/llvm/test/MC/RISCV/tail-call.s @@ -0,0 +1,47 @@ +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELOC %s +# RUN: llvm-mc -triple riscv32 < %s -show-encoding \ +# RUN: | FileCheck -check-prefix=FIXUP %s + +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELOC %s +# RUN: llvm-mc -triple riscv64 < %s -show-encoding \ +# RUN: | FileCheck -check-prefix=FIXUP %s + +.long foo + +tail foo +# RELOC: R_RISCV_CALL foo 0x0 +# INSTR: auipc t1, 0 +# INSTR: jalr t1 +# FIXUP: fixup A - offset: 0, value: foo, kind: +tail bar +# RELOC: R_RISCV_CALL bar 0x0 +# INSTR: auipc t1, 0 +# INSTR: jalr t1 +# FIXUP: fixup A - offset: 0, value: bar, kind: + +# Ensure that tail calls to functions whose names coincide with register names +# work. + +tail zero +# RELOC: R_RISCV_CALL zero 0x0 +# INSTR: auipc t1, 0 +# INSTR: jalr t1 +# FIXUP: fixup A - offset: 0, value: zero, kind: + +tail f1 +# RELOC: R_RISCV_CALL f1 0x0 +# INSTR: auipc t1, 0 +# INSTR: jalr t1 +# FIXUP: fixup A - offset: 0, value: f1, kind: + +tail ra +# RELOC: R_RISCV_CALL ra 0x0 +# INSTR: auipc t1, 0 +# INSTR: jalr t1 +# FIXUP: fixup A - offset: 0, value: ra, kind: |
