[RISCV] Implement pseudo instructions for load/store from a symbol address.

Summary:
Those pseudo-instructions are making load/store instructions able to
load/store from/to a symbol, and its always using PC-relative addressing
to generating a symbol address.

Reviewers: asb, apazos, rogfer01, jrtc27

Differential Revision: https://reviews.llvm.org/D50496

llvm-svn: 354430

8 files changed, 98 insertions, 5 deletions

diff --git a/llvm/test/MC/RISCV/rv32d-invalid.s b/llvm/test/MC/RISCV/rv32d-invalid.s
index d6f5e722f82..f85a0ee13ea 100644
--- a/llvm/test/MC/RISCV/rv32d-invalid.s
+++ b/llvm/test/MC/RISCV/rv32d-invalid.s
@@ -6,8 +6,8 @@ fld ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with
 fsd ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
 
 # Memory operand not formatted correctly
-fld ft1, a0, -200 # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
-fsd ft2, a1, 100 # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
+fld ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+fsd ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
 # Invalid register names
 fld ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32f-invalid.s b/llvm/test/MC/RISCV/rv32f-invalid.s
index 5b49244416b..470035de1ef 100644
--- a/llvm/test/MC/RISCV/rv32f-invalid.s
+++ b/llvm/test/MC/RISCV/rv32f-invalid.s
@@ -6,8 +6,8 @@ flw ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with
 fsw ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
 
 # Memory operand not formatted correctly
-flw ft1, a0, -200 # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
-fsw ft2, a1, 100 # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
+flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
 # Invalid register names
 flw ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s
index b5fabee471e..7cd795b18dc 100644
--- a/llvm/test/MC/RISCV/rv32i-invalid.s
+++ b/llvm/test/MC/RISCV/rv32i-invalid.s
@@ -158,7 +158,7 @@ add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for inst
 sltiu s2, s3, 0x50, 0x60 # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
 
 # Memory operand not formatted correctly
-lw a4, a5, 111 # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
+lw a4, a5, 111 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
 
 # Too few operands
 ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64i-pseudos.s b/llvm/test/MC/RISCV/rv64i-pseudos.s
new file mode 100644
index 00000000000..2814776e8ee
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64i-pseudos.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mc %s -triple=riscv64 | FileCheck %s
+
+# CHECK: .Lpcrel_hi0:
+# CHECK: auipc a2, %pcrel_hi(a_symbol)
+# CHECK: lwu  a2, %pcrel_lo(.Lpcrel_hi0)(a2)
+lwu a2, a_symbol
+
+# CHECK: .Lpcrel_hi1:
+# CHECK: auipc a3, %pcrel_hi(a_symbol)
+# CHECK: ld  a3, %pcrel_lo(.Lpcrel_hi1)(a3)
+ld a3, a_symbol
+
+# CHECK: .Lpcrel_hi2:
+# CHECK: auipc a4, %pcrel_hi(a_symbol)
+# CHECK: sd  a3, %pcrel_lo(.Lpcrel_hi2)(a4)
+sd a3, a_symbol, a4
diff --git a/llvm/test/MC/RISCV/rvd-pseudos.s b/llvm/test/MC/RISCV/rvd-pseudos.s
new file mode 100644
index 00000000000..5c146cacb2a
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvd-pseudos.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+d | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+d | FileCheck %s
+
+# CHECK: .Lpcrel_hi0:
+# CHECK: auipc a2, %pcrel_hi(a_symbol)
+# CHECK: fld  fa2, %pcrel_lo(.Lpcrel_hi0)(a2)
+fld fa2, a_symbol, a2
+
+# CHECK: .Lpcrel_hi1:
+# CHECK: auipc a3, %pcrel_hi(a_symbol)
+# CHECK: fsd  fa2, %pcrel_lo(.Lpcrel_hi1)(a3)
+fsd fa2, a_symbol, a3
diff --git a/llvm/test/MC/RISCV/rvf-pseudos.s b/llvm/test/MC/RISCV/rvf-pseudos.s
new file mode 100644
index 00000000000..5907adf5bf4
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvf-pseudos.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+f | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+f | FileCheck %s
+
+# CHECK: .Lpcrel_hi0:
+# CHECK: auipc a2, %pcrel_hi(a_symbol)
+# CHECK: flw  fa2, %pcrel_lo(.Lpcrel_hi0)(a2)
+flw fa2, a_symbol, a2
+
+# CHECK: .Lpcrel_hi1:
+# CHECK: auipc a3, %pcrel_hi(a_symbol)
+# CHECK: fsw  fa2, %pcrel_lo(.Lpcrel_hi1)(a3)
+fsw fa2, a_symbol, a3
diff --git a/llvm/test/MC/RISCV/rvi-pseudos-invalid.s b/llvm/test/MC/RISCV/rvi-pseudos-invalid.s
index 2ce12490dec..5d983c0011d 100644
--- a/llvm/test/MC/RISCV/rvi-pseudos-invalid.s
+++ b/llvm/test/MC/RISCV/rvi-pseudos-invalid.s
@@ -20,3 +20,10 @@ la x1, %hi(1234) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol nam
 la x1, %lo(1234) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
 la x1, %hi(foo) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
 la x1, %lo(foo) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
+
+sw a2, %hi(a_symbol), a3 # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
+sw a2, %lo(a_symbol), a3 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+sw a2, %lo(a_symbol)(a4), a3 # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
+
+# Too few operands must be rejected
+sw a2, a_symbol # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rvi-pseudos.s b/llvm/test/MC/RISCV/rvi-pseudos.s
index 5b2ac275c99..41e6e9c3185 100644
--- a/llvm/test/MC/RISCV/rvi-pseudos.s
+++ b/llvm/test/MC/RISCV/rvi-pseudos.s
@@ -71,3 +71,49 @@ la a3, ra
 # CHECK-PIC-RV32: lw    a4, %pcrel_lo(.Lpcrel_hi9)(a4)
 # CHECK-PIC-RV64: ld    a4, %pcrel_lo(.Lpcrel_hi9)(a4)
 la a4, f1
+
+# CHECK: .Lpcrel_hi10:
+# CHECK: auipc a0, %pcrel_hi(a_symbol)
+# CHECK: lb  a0, %pcrel_lo(.Lpcrel_hi10)(a0)
+lb a0, a_symbol
+
+# CHECK: .Lpcrel_hi11:
+# CHECK: auipc a1, %pcrel_hi(a_symbol)
+# CHECK: lh  a1, %pcrel_lo(.Lpcrel_hi11)(a1)
+lh a1, a_symbol
+
+# CHECK: .Lpcrel_hi12:
+# CHECK: auipc a2, %pcrel_hi(a_symbol)
+# CHECK: lhu  a2, %pcrel_lo(.Lpcrel_hi12)(a2)
+lhu a2, a_symbol
+
+# CHECK: .Lpcrel_hi13:
+# CHECK: auipc a3, %pcrel_hi(a_symbol)
+# CHECK: lw  a3, %pcrel_lo(.Lpcrel_hi13)(a3)
+lw a3, a_symbol
+
+# CHECK: .Lpcrel_hi14:
+# CHECK: auipc a4, %pcrel_hi(a_symbol)
+# CHECK: sb  a3, %pcrel_lo(.Lpcrel_hi14)(a4)
+sb a3, a_symbol, a4
+
+# CHECK: .Lpcrel_hi15:
+# CHECK: auipc a4, %pcrel_hi(a_symbol)
+# CHECK: sh  a3, %pcrel_lo(.Lpcrel_hi15)(a4)
+sh a3, a_symbol, a4
+
+# CHECK: .Lpcrel_hi16:
+# CHECK: auipc a4, %pcrel_hi(a_symbol)
+# CHECK: sw  a3, %pcrel_lo(.Lpcrel_hi16)(a4)
+sw a3, a_symbol, a4
+
+# Check that we can load the address of symbols that are spelled like a register
+# CHECK: .Lpcrel_hi17:
+# CHECK: auipc a2, %pcrel_hi(zero)
+# CHECK: lw  a2, %pcrel_lo(.Lpcrel_hi17)(a2)
+lw a2, zero
+
+# CHECK: .Lpcrel_hi18:
+# CHECK: auipc a4, %pcrel_hi(zero)
+# CHECK: sw  a3, %pcrel_lo(.Lpcrel_hi18)(a4)
+sw a3, zero, a4