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| author | Alex Bradbury <asb@lowrisc.org> | 2018-11-30 13:39:17 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-11-30 13:39:17 +0000 |
| commit | 26403def69f72c7938889c1902d62121095b93d7 (patch) | |
| tree | c9f4b11365acabe8cf237ff3cb83d335e0a40ad8 /llvm/test/MC/RISCV | |
| parent | ebf787b138841056ac1c4c2130f35420dfed22f4 (diff) | |
| download | bcm5719-llvm-26403def69f72c7938889c1902d62121095b93d7.tar.gz bcm5719-llvm-26403def69f72c7938889c1902d62121095b93d7.zip | |
[RISCV] Add UNIMP instruction (32- and 16-bit forms)
This patch adds support for UNIMP in both 32- and 16-bit forms. The 32-bit
form can be seen as a variant of the ECALL/EBREAK/etc. family of instructions.
The 16-bit form is just all zeroes, which isn't a valid RISC-V instruction,
but still follows the 16-bit instruction form (i.e. bits 0-1 != 11).
Until recently unimp was undocumented and supported just by binutils, which
printed unimp for either the 16 or 32-bit form. Both forms are now documented
<https://github.com/riscv/riscv-asm-manual/pull/20> and binutils now supports
c.unimp <https://sourceware.org/ml/binutils-cvs/2018-11/msg00179.html>.
Differential Revision: https://reviews.llvm.org/D54316
Patch by Luís Marques.
llvm-svn: 347988
Diffstat (limited to 'llvm/test/MC/RISCV')
| -rw-r--r-- | llvm/test/MC/RISCV/compress-rv32i.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv32c-valid.s | 3 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv32i-valid.s | 3 |
3 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/MC/RISCV/compress-rv32i.s b/llvm/test/MC/RISCV/compress-rv32i.s index 0436a99e5ba..149279c4330 100644 --- a/llvm/test/MC/RISCV/compress-rv32i.s +++ b/llvm/test/MC/RISCV/compress-rv32i.s @@ -211,3 +211,9 @@ add s0, s0, a5 # CHECK-INST: c.swsp zero, 252(sp) # CHECK: # encoding: [0x82,0xdf] sw zero, 252(sp) + +# CHECK-BYTES: 00 00 +# CHECK-ALIAS: unimp +# CHECK-INST: c.unimp +# CHECK: # encoding: [0x00,0x00] +unimp diff --git a/llvm/test/MC/RISCV/rv32c-valid.s b/llvm/test/MC/RISCV/rv32c-valid.s index c761c712789..b72e4922a57 100644 --- a/llvm/test/MC/RISCV/rv32c-valid.s +++ b/llvm/test/MC/RISCV/rv32c-valid.s @@ -103,3 +103,6 @@ c.lui s0, 0xfffe0 # CHECK-ASM-AND-OBJ: c.lui s0, 1048575 # CHECK-ASM: encoding: [0x7d,0x74] c.lui s0, 0xfffff +# CHECK-ASM-AND-OBJ: c.unimp +# CHECK-ASM: encoding: [0x00,0x00] +c.unimp diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s index 816aa275fe1..0df53e661b9 100644 --- a/llvm/test/MC/RISCV/rv32i-valid.s +++ b/llvm/test/MC/RISCV/rv32i-valid.s @@ -248,6 +248,9 @@ ecall # CHECK-ASM-AND-OBJ: ebreak # CHECK-ASM: encoding: [0x73,0x00,0x10,0x00] ebreak +# CHECK-ASM-AND-OBJ: unimp +# CHECK-ASM: encoding: [0x73,0x10,0x00,0xc0] +unimp # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 # CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff] |
