Recommit: "[mips] Add rsqrt, recip for MIPS"

Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.

Reviewers: vkalintiris, zoran.jovanoic

Differential Review: https://reviews.llvm.org/D24499

llvm-svn: 283334

30 files changed, 91 insertions, 35 deletions

diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
index cc391934c5a..84f498754cd 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
@@ -195,3 +195,7 @@
 0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10)
 0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6)
 0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6)
+0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6
+0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30
+0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28
+0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
index 894ac6e048f..3be26bb5b66 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
@@ -199,3 +199,7 @@
 0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
 0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
 0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
+0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6
+0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30
+0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28
+0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
index 82a883557e8..5a374ac43cb 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
@@ -135,8 +135,12 @@
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
index 7ee4f4bf7fa..9935929a1cc 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -286,6 +286,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
index da8130c9f4c..bc7ae8dd839 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
@@ -70,13 +70,9 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
index 37c14de4cb6..96c7805e216 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
@@ -129,10 +129,14 @@
 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
index 8e5c16b4a33..9be0189e6bf 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
@@ -283,6 +283,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
index 7623bba364f..5d317edd465 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
@@ -70,13 +70,9 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
index b68089b0a07..072e17b6151 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
@@ -131,8 +131,12 @@
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
index afe1b695dea..ecb64ccdea2 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
@@ -284,6 +284,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
index 27f5498ea66..ed9bc08d72d 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
@@ -70,13 +70,9 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
index 34bfd769f2d..271ff904f17 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
@@ -125,8 +125,12 @@
 0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4
 0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4
 0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
 0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index 7266848706d..b796f48d566 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -134,6 +134,10 @@
 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x42 0x00 0x00 0x58 # CHECK: eretnc
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 8 but the disassembler currently emits 12
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
index 4a3d78cde55..64c350e45a8 100644
--- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
@@ -155,11 +155,15 @@
 0x27 0x38 0x07 0x00 # CHECK: nor $7, $zero, $7
 0x25 0x60 0x1d 0x02 # CHECK: or $12, $16, $sp
 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
-0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5) 
+0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5)
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
 0x8c 0x21 0x20 0x46 # CHECK: round.w.d $f6, $f4
 0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0x6f 0xb2 0xd6 0xa1 # CHECK: sb $22, -19857($14)
 0xd8 0x49 0x6f 0xe2 # CHECK: sc $15, 18904($19)
 0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
index f225d2cc220..2635b6bca7d 100644
--- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
@@ -257,3 +257,7 @@
 0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13)
 0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18)
 0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10)
+0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
index 3375bcf3140..1b669389e7b 100644
--- a/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
@@ -36,7 +36,3 @@
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
-0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
index 1cd7b0bceba..eb531aad882 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
@@ -206,6 +206,10 @@
 0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
 0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
 0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
 0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
 0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt
index dd97bcd5a1f..bb6807a25da 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt
@@ -73,8 +73,4 @@
 0x46 0xdd 0xd0 0x6d # CHECK: plu.ps $f1, $f26, $f29
 0x46 0xda 0xf2 0x6e # CHECK: pul.ps $f9, $f30, $f26
 0x46 0xc2 0x4e 0x2f # CHECK: puu.ps $f24, $f9, $f2
-0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x41 # CHECK: sub.ps $f5, $f14, $f26
diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
index 5b5427db1e1..8a6bf0ce613 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
@@ -331,6 +331,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
index 3f2b7615eb3..cc74ce95ae3 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -193,12 +193,16 @@
 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
index 5de751234c8..ab857a55c7b 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
@@ -363,6 +363,10 @@
 0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736
 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
 0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
index cbc2eee3fe1..145dcacb1f5 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
@@ -67,10 +67,6 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
index 7d59ef6d3e0..31618400d93 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -190,12 +190,16 @@
 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
index 01c02ad8222..7dd8d64f5c0 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -351,8 +351,12 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
-0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
-0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
+0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27   
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
index 8c58eb1c9e3..74ae59669f5 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
@@ -67,10 +67,6 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
index ee6ad1c7194..5cc0aa6b716 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -190,12 +190,16 @@
 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
index 12e5294d36d..f2467e8e480 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -351,6 +351,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
index b8a98bdf73e..2d02fca4b7c 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
@@ -67,10 +67,6 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
index cda52962483..15821640ff3 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -156,8 +156,12 @@
 0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
 0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19)
 0xa7 0xe6 0xaf 0x7f # CHECK: scd $15, -51($sp)
 0x0e 0x00 0x00 0x00 # CHECK: sdbbp
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 7be3fa71b1e..066c3d4a273 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -153,6 +153,10 @@
 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x42 0x00 0x00 0x58 # CHECK: eretnc
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 8 but the disassembler currently emits 12