[PPC64] Add vector pack/unpack support from ISA 2.07

This patch adds support for the following new instructions in the
Power ISA 2.07:

  vpksdss
  vpksdus
  vpkudus
  vpkudum
  vupkhsw
  vupklsw

These instructions are available through the vec_packs, vec_packsu,
vec_unpackh, and vec_unpackl built-in interfaces.  These are
lane-sensitive instructions, so the built-ins have different
implementations for big- and little-endian, and the instructions must
be marked as killing the vector swap optimization for now.

The first three instructions perform saturating pack operations.  The
fourth performs a modulo pack operation, which means it can be
represented with a vector shuffle, and conversely the appropriate
vector shuffles may cause this instruction to be generated.  The other
instructions are only generated via built-in support for now.

Appropriate tests have been added.

There is a companion patch to clang for the rest of this support.

llvm-svn: 237499

1 files changed, 19 insertions, 0 deletions

diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt
new file mode 100644
index 00000000000..eeea2db673f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt
@@ -0,0 +1,19 @@
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr8 | FileCheck %s
+
+# CHECK: vpksdss 2, 3, 4
+0x10 0x43 0x25 0xce
+
+# CHECK: vpksdus 2, 3, 4
+0x10 0x43 0x25 0x4e
+
+# CHECK: vpkudus 2, 3, 4
+0x10 0x43 0x24 0xce
+
+# CHECK: vpkudum 2, 3, 4
+0x10 0x43 0x24 0x4e
+
+# CHECK: vupkhsw 2, 3
+0x10 0x40 0x1e 0x4e
+
+# CHECK: vupklsw 2, 3
+0x10 0x40 0x1e 0xce